From 2e984ab48e2cc51dfc48a8bcbdc8f7af177c707c Mon Sep 17 00:00:00 2001 From: morgan Date: Mon, 2 Sep 2024 16:50:04 +0800 Subject: [PATCH] cxp: move debug buffer out of tx_command_packet --- src/gateware/cxp.py | 84 ++++++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index f41d6a6..7a8f0d8 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -9,7 +9,6 @@ from cxp_pipeline import * class CXP(Module, AutoCSR): def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads): self.submodules.txtrig = TX_Trigger() - self.submodules.txcore = TX_Command_Packet(pmod_pads) self.submodules.upconn = UpConn_Packets(upconn_pads, sys_clk_freq, debug_sma, pmod_pads) @@ -73,6 +72,39 @@ class UpConn_Packets(Module, AutoCSR): # Table 54 (CXP-001-2021) # Largest CXP register is 8 byte + self.submodules.tx_command = tx_command = TX_Command_Packet(pmod_pads) + + + # DEBUG: OUTPUT + self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64) + self.comb += tx_command.source.connect(buf_out.sink) + + self.inc = CSR() + self.dout_pak = CSRStatus(8) + self.kout_pak = CSRStatus() + self.dout_valid = CSRStatus() + + self.sync += [ + # output + buf_out.source.ack.eq(self.inc.re), + self.dout_pak.status.eq(buf_out.source.data), + self.kout_pak.status.eq(buf_out.source.k), + self.dout_valid.status.eq(buf_out.source.stb), + ] + + self.specials += [ + # pmod 0-7 pin + Instance("OBUF", i_I=tx_command.buf_in.sink.stb, o_O=pmod_pads[0]), + Instance("OBUF", i_I=tx_command.buf_in.sink.ack, o_O=pmod_pads[1]), + Instance("OBUF", i_I=tx_command.buf_in.source.stb, o_O=pmod_pads[2]), + Instance("OBUF", i_I=tx_command.buf_in.source.ack, o_O=pmod_pads[3]), + Instance("OBUF", i_I=buf_out.sink.stb, o_O=pmod_pads[4]), + Instance("OBUF", i_I=buf_out.sink.ack, o_O=pmod_pads[5]), + Instance("OBUF", i_I=buf_out.source.stb, o_O=pmod_pads[6]), + Instance("OBUF", i_I=buf_out.source.ack, o_O=pmod_pads[7]), + ] + + self.symbol2 = CSR(9) self.sync += [ upconn_phy.tx_fifos.sink[2].stb.eq(self.symbol2.re), @@ -126,7 +158,7 @@ class TX_Command_Packet(Module, AutoCSR): self.packet_type = CSRStorage(8) self.din_len = CSRStorage(6) - self.din_pak = CSR(8) + self.din_data = CSR(8) self.din_k = CSRStorage() self.din_ready = CSRStatus() @@ -136,24 +168,16 @@ class TX_Command_Packet(Module, AutoCSR): # a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available # otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source self.submodules.buf_in = buf_in = stream.SyncFIFO(cxp_phy_layout(), 2) - self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64) self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout()) self.submodules.pak_type = pak_type = Code_Inserter(cxp_phy_layout()) self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(cxp_phy_layout()) - - self.comb += [ - pak_type.data.eq(self.packet_type.storage), - pak_type.k.eq(0), - ] len = Signal(6, reset=1) self.sync += [ - - # input self.din_ready.status.eq(buf_in.sink.ack), buf_in.sink.stb.eq(0), - If(self.din_pak.re, + If(self.din_data.re, If(len == self.din_len.storage, len.eq(len.reset), buf_in.sink.eop.eq(1), @@ -162,41 +186,23 @@ class TX_Command_Packet(Module, AutoCSR): buf_in.sink.eop.eq(0), ), buf_in.sink.stb.eq(1), - buf_in.sink.data.eq(self.din_pak.r), + buf_in.sink.data.eq(self.din_data.r), buf_in.sink.k.eq(self.din_k.storage), ), ] + + self.comb += [ + pak_type.data.eq(self.packet_type.storage), + pak_type.k.eq(0), + ] - tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp, buf_out] + tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp] for s, d in zip(tx_pipeline, tx_pipeline[1:]): self.comb += s.source.connect(d.sink) - - # DEBUG - self.inc = CSR() - self.dout_pak = CSRStatus(8) - self.kout_pak = CSRStatus() - self.dout_valid = CSRStatus() - - self.sync += [ - # output - buf_out.source.ack.eq(self.inc.re), - self.dout_pak.status.eq(buf_out.source.data), - self.kout_pak.status.eq(buf_out.source.k), - self.dout_valid.status.eq(buf_out.source.stb), - ] - - self.specials += [ - # pmod 0-7 pin - Instance("OBUF", i_I=buf_in.sink.stb, o_O=pmod_pads[0]), - Instance("OBUF", i_I=buf_in.sink.ack, o_O=pmod_pads[1]), - Instance("OBUF", i_I=buf_in.source.stb, o_O=pmod_pads[2]), - Instance("OBUF", i_I=buf_in.source.ack, o_O=pmod_pads[3]), - Instance("OBUF", i_I=buf_out.sink.stb, o_O=pmod_pads[4]), - Instance("OBUF", i_I=buf_out.sink.ack, o_O=pmod_pads[5]), - Instance("OBUF", i_I=buf_out.source.stb, o_O=pmod_pads[6]), - Instance("OBUF", i_I=buf_out.source.ack, o_O=pmod_pads[7]), - ] + self.source = tx_pipeline[-1].source + +