forked from M-Labs/artiq-zynq
cxp pipeline: packet handling pipeline
tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add fifo to store control packet rx pipeline: add reciever path rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checker
This commit is contained in:
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
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import struct
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upconn_dw = 8
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upconn_layout = [("data", upconn_dw), ("k", upconn_dw//8)]
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downconn_dw = 32
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downconn_layout = [("data", downconn_dw), ("k", downconn_dw//8)]
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def K(x, y):
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return ((y << 5) | x)
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KCode = {
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"pak_start" : K(27, 7),
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"io_ack" : K(28, 6),
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"trig_indic_28_2" : K(28, 2),
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"trig_indic_28_4" : K(28, 4),
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"pak_end" : K(29, 7),
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}
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def _bytes2word(bytes, big_endian=True):
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if big_endian:
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return struct.unpack(">I", struct.pack(">4B", *bytes))[0]
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else:
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return struct.unpack("<I", struct.pack(">4B", *bytes))[0]
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class Code_Source(Module):
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def __init__(self, layout, data, k):
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self.source = stream.Endpoint(layout)
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self.stb = Signal()
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# # #
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assert len(data) == len(k) > 0
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counts = len(data)
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cnt = Signal() if counts == 1 else Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(self.stb,
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NextState("WRITE")
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)
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)
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fsm.act("WRITE",
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self.source.stb.eq(1),
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self.source.data.eq(Array(data)[cnt]),
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self.source.k.eq(Array(k)[cnt]),
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If(cnt == counts - 1,
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self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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)
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class Code_Inserter(Module):
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def __init__(self, layout, data, k, insert_infront=True):
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self.sink = stream.Endpoint(layout)
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self.source = stream.Endpoint(layout)
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self.data = Signal.like(self.sink.data)
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self.k = Signal.like(self.sink.k)
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# # #
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assert len(data) == len(k) > 0
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counts = len(data)
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cnt = Signal() if counts == 1 else Signal(max=counts)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += [
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If(clr_cnt,
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cnt.eq(cnt.reset),
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).Elif(inc_cnt,
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cnt.eq(cnt + 1),
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)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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remove_sink_oep = 0 if insert_infront else 1
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# add code in front: IDLE -> INSERT -> COPY
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# add code at end: IDLE -> COPY -> INSERT
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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clr_cnt.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT" if insert_infront else "COPY"),
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)
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)
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fsm.act("INSERT",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Array(data)[cnt]),
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self.source.k.eq(Array(k)[cnt]),
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If(cnt == counts - 1,
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If(remove_sink_oep, self.source.eop.eq(1)),
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If(self.source.ack, NextState("COPY" if insert_infront else "IDLE"))
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).Else(
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inc_cnt.eq(self.source.ack)
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)
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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If(remove_sink_oep, self.source.eop.eq(0)),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("IDLE" if insert_infront else "INSERT"),
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)
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)
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class Packet_Wrapper(Module):
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def __init__(self, layout):
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self.submodules.pak_start = pak_start = Code_Inserter(layout, [KCode["pak_start"]]*4, [1]*4)
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self.submodules.pak_end = pak_end = Code_Inserter(layout, [KCode["pak_end"]]*4, [1]*4, insert_infront=False)
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self.comb += pak_start.source.connect(pak_end.sink),
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self.sink = pak_start.sink
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self.source = pak_end.source
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width-1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.data.eq(self.data),
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self.engine.last.eq(reg),
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self.value.eq(reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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class CXPCRC32Checker(LiteEthMACCRCChecker):
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def __init__(self, layout):
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LiteEthMACCRCChecker.__init__(self, CXPCRC32, layout)
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class TX_Trigger(Module, AutoCSR):
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def __init__(self):
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self.trig_stb = Signal()
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self.delay = Signal(upconn_dw)
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self.linktrig_mode = Signal(max=4)
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# # #
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# Table 15 & 16 (CXP-001-2021)
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# Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet
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self.submodules.code_src = code_src = Code_Source(upconn_layout, [self.delay]*3, [0]*3)
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self.comb += code_src.stb.eq(self.trig_stb),
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header = [Signal(8) for _ in range(3)]
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self.comb += \
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If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
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header[0].eq(KCode["trig_indic_28_2"]),
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header[1].eq(KCode["trig_indic_28_4"]),
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header[2].eq(KCode["trig_indic_28_4"]),
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).Else(
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header[0].eq(KCode["trig_indic_28_4"]),
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header[1].eq(KCode["trig_indic_28_2"]),
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header[2].eq(KCode["trig_indic_28_2"]),
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)
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self.submodules.inserter = inserter = Code_Inserter(upconn_layout, header, [1]*3)
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self.comb += code_src.source.connect(inserter.sink)
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self.source = inserter.source
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class Trigger_ACK(Module):
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def __init__(self):
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self.ack = Signal()
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# # #
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# Section 9.3.2 (CXP-001-2021)
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# Send 4x K28.6 and 4x 0x01 as trigger packet ack
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self.submodules.code_src = code_src = Code_Source(upconn_layout, [0x01]*4, [0]*4)
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self.submodules.inserter = inserter = Code_Inserter(upconn_layout, [KCode["io_ack"]]*4, [1]*4)
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self.comb += [
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code_src.stb.eq(self.ack),
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code_src.source.connect(inserter.sink)
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]
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self.source = inserter.source
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class TX_Command_Packet(Module, AutoCSR):
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# Section 12.1.2 (CXP-001-2021)
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# Max control packet size is 128 bytes
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def __init__(self, fifo_depth=128):
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self.len = CSRStorage(log2_int(fifo_depth))
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self.data = CSR(upconn_dw)
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self.writeable = CSRStatus()
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# # #
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self.submodules.fifo = fifo = stream.SyncFIFO(upconn_layout, fifo_depth)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
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self.source = pak_wrp.source
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self.comb += fifo.source.connect(pak_wrp.sink)
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cnt = Signal(log2_int(fifo_depth), reset=1)
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self.sync += [
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self.writeable.status.eq(fifo.sink.ack),
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If(fifo.sink.ack, fifo.sink.stb.eq(0)),
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If(self.data.re,
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fifo.sink.stb.eq(1),
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fifo.sink.data.eq(self.data.r),
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fifo.sink.k.eq(0),
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If(cnt == self.len.storage,
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fifo.sink.eop.eq(1),
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cnt.eq(cnt.reset),
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).Else(
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fifo.sink.eop.eq(0),
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cnt.eq(cnt + 1),
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),
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)
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]
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class TX_Test_Packet(Module, AutoCSR):
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def __init__(self):
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self.stb = CSR()
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self.busy = CSRStatus()
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# # #
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self.submodules.test_pattern_src = test_pattern_src = Code_Source(upconn_layout, [*range(0x100)]*16, [0]*0x100*16)
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self.submodules.pak_type_inserter = pak_type_inserter = Code_Inserter(upconn_layout, [0x04]*4, [0]*4)
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self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(upconn_layout)
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self.comb += [
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test_pattern_src.source.connect(pak_type_inserter.sink),
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pak_type_inserter.source.connect(pak_wrp.sink),
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]
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self.source = pak_wrp.source
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self.sync += [
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test_pattern_src.stb.eq(self.stb.re),
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If(self.stb.re,
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self.busy.status.eq(1),
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).Elif(self.source.eop & self.source.ack,
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self.busy.status.eq(0)
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)
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]
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class RX_Debug_Buffer(Module,AutoCSR):
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def __init__(self):
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self.submodules.buf_out = buf_out = stream.SyncFIFO(downconn_layout, 128)
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self.sink = buf_out.sink
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self.inc = CSR()
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self.dout_pak = CSRStatus(downconn_dw)
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self.kout_pak = CSRStatus(downconn_dw//8)
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self.dout_valid = CSRStatus()
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self.sync += [
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# output
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buf_out.source.ack.eq(self.inc.re),
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self.dout_pak.status.eq(buf_out.source.data),
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self.kout_pak.status.eq(buf_out.source.k),
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class Receiver_Path(Module, AutoCSR):
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def __init__(self):
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self.trig_ack = Signal()
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self.trig_clr = Signal()
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self.packet_type = Signal(8)
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self.decoder_err = Signal()
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self.decoder_err_clr = Signal()
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self.test_err = Signal()
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self.test_err_clr = Signal()
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# # #
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self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
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self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
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# Error are latched
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self.sync += [
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If(trig_ack_checker.ack,
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self.trig_ack.eq(1),
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).Elif(self.trig_clr,
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self.trig_ack.eq(0),
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),
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If(packet_decoder.decode_err,
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self.decoder_err.eq(1),
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).Elif(self.decoder_err_clr,
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self.decoder_err.eq(0),
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),
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If(packet_decoder.test_err,
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self.test_err.eq(1),
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).Elif(self.test_err_clr,
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self.test_err.eq(0),
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)
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]
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self.comb += [
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self.packet_type.eq(packet_decoder.packet_type),
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]
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pipeline = [ trig_ack_checker, packet_decoder ]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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class CXP_Data_Packet_Decode(Module):
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def __init__(self):
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self.sink = stream.Endpoint(downconn_layout)
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# This is where data stream comes out
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self.source = stream.Endpoint(downconn_layout)
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self.packet_type = Signal(8)
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self.decode_err = Signal()
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self.buffer = Signal(40*downconn_dw)
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self.test_err = Signal()
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# # #
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# decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
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type = {
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"data_stream": 0x01,
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"control_ack_no_tag": 0x03,
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"test_packet": 0x04,
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"control_ack_with_tag": 0x06,
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"event_ack": 0x08,
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"heartbeat": 0x09,
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"debug" : 0x02,
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}
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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# TODO: add error correction?
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If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_start"]]*4)) & (self.sink.k == 0b1111)),
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NextState("DECODE"),
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)
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)
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# TODO: decode all packet type here
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cnt = Signal(max=0x100)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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NextValue(self.packet_type, self.sink.data[:8]),
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Case(self.sink.data[:8],{
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type["data_stream"]: NextState("STREAMING"),
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type["debug"]: NextState("STREAMING"),
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type["test_packet"]: [
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NextValue(cnt, 0),
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NextState("VERIFY_TEST_PATTERN"),
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],
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"default": [
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self.decode_err.eq(1),
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# wait till next valid packet
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NextState("IDLE"),
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],
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}),
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)
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)
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# Section 9.9.1 (CXP-001-2021)
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# the received test data packet (0x00, 0x01 ... 0xFF)
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# need to be compared against the local test sequence generator
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fsm.act("VERIFY_TEST_PATTERN",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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If(((self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
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NextState("IDLE"),
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).Else(
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If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),
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self.test_err.eq(1),
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),
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If(cnt == 0xFC,
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NextValue(cnt, cnt.reset),
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).Else(
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NextValue(cnt, cnt + 4)
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)
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)
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)
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)
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fsm.act("STREAMING",
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If((self.sink.stb & (self.sink.data == _bytes2word([KCode["pak_end"]]*4)) & (self.sink.k == 0b1111)),
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# discard K29,7
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self.sink.ack.eq(1),
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NextState("IDLE")
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).Else(
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self.sink.connect(self.source),
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)
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)
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# # input pipeline stage - determine packet length based on type
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# self.sync += [
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# packet_start.eq((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1)),
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# packet_end.eq((self.sink.data[0] == K(29, 7)) & (self.sink.k[0] == 1)),
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|
||||
# If((self.sink.data[0] == K(27, 7)) & (self.sink.k[0] == 1),
|
||||
# packet_buffer_load.eq(1),
|
||||
# ),
|
||||
|
||||
|
||||
# trig_ack.eq((self.sink.data[0] == K(28, 6)) & (self.sink.k[0] == 1)),
|
||||
# If(trig_ack,
|
||||
# self.trig_ack.eq(self.sink.data[0]),
|
||||
# trig_ack.eq(0),
|
||||
# ).Elif(packet_buffer_load,
|
||||
# # TODO: add test packet counting
|
||||
# Case(buffer_count,
|
||||
# {i: buffer[i*downconn_dw:(i+1)*downconn_dw].eq(self.sink.data)
|
||||
# for i in range(40)}),
|
||||
# buffer_count.eq(buffer_count + 1),
|
||||
|
||||
|
||||
class CXP_Trig_Ack_Checker(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self.sink = stream.Endpoint(downconn_layout)
|
||||
self.source = stream.Endpoint(downconn_layout)
|
||||
|
||||
self.ack = Signal()
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
|
||||
fsm.act("IDLE",
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.stb,
|
||||
self.sink.ack.eq(0),
|
||||
NextState("COPY"),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("COPY",
|
||||
If((self.sink.stb & (self.sink.data == _bytes2word([KCode["io_ack"]]*4)) & (self.sink.k == 0b1111)),
|
||||
# discard K28,6
|
||||
self.sink.ack.eq(1),
|
||||
NextState("CHECK_ACK")
|
||||
).Else(
|
||||
self.sink.connect(self.source),
|
||||
)
|
||||
)
|
||||
|
||||
fsm.act("CHECK_ACK",
|
||||
If(self.sink.stb,
|
||||
NextState("IDLE"),
|
||||
# discard the word after K28,6
|
||||
self.sink.ack.eq(1),
|
||||
If(self.sink.data == _bytes2word([0x01]*4),
|
||||
self.ack.eq(1),
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue