forked from M-Labs/artiq-zynq
cxp downconn: cleanup & add reason for comma_det
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@ -286,8 +286,8 @@ class QPLL(Module):
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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# compared to the usual 8b10b binary representation.
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class Comma_Detector(Module):
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class Comma_Detector(Module):
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def __init__(self, comma, check_period=100_000, width=20):
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def __init__(self, comma, check_period=100_000):
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self.data = Signal(width)
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self.data = Signal(20)
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self.rxinit_done = Signal()
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self.rxinit_done = Signal()
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self.aligner_en_rxclk = Signal()
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self.aligner_en_rxclk = Signal()
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@ -296,6 +296,12 @@ class Comma_Detector(Module):
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# # #
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# # #
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# The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
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# - UG476 (v1.12.1) p.228
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# The validity of data & comma are checked externally
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aligned = Signal()
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aligned = Signal()
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valid_data = Signal()
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valid_data = Signal()
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aligned_rxclk = Signal()
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aligned_rxclk = Signal()
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@ -308,7 +314,6 @@ class Comma_Detector(Module):
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self.submodules.check_ps = check_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
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self.submodules.check_ps = check_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
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comma_n = ~comma & 0b1111111111
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comma_n = ~comma & 0b1111111111
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self.sync.cxp_gtx_rx += [
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self.sync.cxp_gtx_rx += [
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If(check_ps.o,
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If(check_ps.o,
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aligned_rxclk.eq(0),
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aligned_rxclk.eq(0),
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@ -327,7 +332,6 @@ class Comma_Detector(Module):
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check_counter = Signal(reset=check_period-1, max=check_period)
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check_counter = Signal(reset=check_period-1, max=check_period)
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check = Signal()
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check = Signal()
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self.sync += [
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self.sync += [
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check.eq(0),
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check.eq(0),
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If(check_counter == 0,
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If(check_counter == 0,
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@ -338,12 +342,11 @@ class Comma_Detector(Module):
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)
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)
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]
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_COMMA_ALIGN")
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aligner_en = Signal()
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aligner_en = Signal()
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self.specials += MultiReg(aligner_en, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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self.specials += MultiReg(aligner_en, self.aligner_en_rxclk, odomain="cxp_gtx_rx")
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fsm.act("WAIT_COMMA_ALIGN",
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fsm.act("IDLE",
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aligner_en.eq(1),
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aligner_en.eq(1),
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If(check,
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If(check,
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check_ps.i.eq(1),
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check_ps.i.eq(1),
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@ -363,7 +366,7 @@ class Comma_Detector(Module):
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NextState("READY"),
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NextState("READY"),
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).Else(
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).Else(
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self.restart.eq(1),
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self.restart.eq(1),
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NextState("IDLE"),
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NextState("WAIT_COMMA_ALIGN"),
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)
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)
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)
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)
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)
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)
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@ -374,7 +377,7 @@ class Comma_Detector(Module):
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check_ps.i.eq(1),
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check_ps.i.eq(1),
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If(~(aligned & valid_data),
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If(~(aligned & valid_data),
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self.restart.eq(1),
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self.restart.eq(1),
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NextState("IDLE"),
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NextState("WAIT_COMMA_ALIGN"),
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)
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)
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)
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)
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)
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)
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@ -564,7 +567,7 @@ class GTX(Module):
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# RX Byte and Word Alignment Attributes
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_WORD=2, # allow rxslide to shift 20 times
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p_ALIGN_COMMA_WORD=2, # align comma to rxdata[:10] only
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_DET="TRUE",
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@ -575,7 +578,7 @@ class GTX(Module):
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p_RX_SIG_VALID_DLY=10,
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p_RX_SIG_VALID_DLY=10,
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i_RXPCOMMAALIGNEN=comma_aligner_en,
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i_RXPCOMMAALIGNEN=comma_aligner_en,
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i_RXMCOMMAALIGNEN=comma_aligner_en,
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i_RXMCOMMAALIGNEN=comma_aligner_en,
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i_RXCOMMADETEN=1, # enable auto word alignment
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i_RXCOMMADETEN=1,
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# RX 8B/10B Decoder Attributes
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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