forked from M-Labs/artiq-zynq
cxp GW: add mem size getter for each mem region
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485739404f
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@ -25,14 +25,20 @@ class CXP_Interface(Module, AutoCSR):
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def get_tx_port(self):
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def get_tx_port(self):
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return self.upconn.command.mem.get_port(write_capable=True)
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return self.upconn.command.mem.get_port(write_capable=True)
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def get_tx_mem_size(self):
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return self.upconn.command.mem.depth*self.upconn.command.mem.width
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def get_rx_port(self):
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def get_rx_port(self):
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return self.downconn.packet_decoder.mem.get_port(write_capable=False)
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return self.downconn.packet_decoder.mem.get_port(write_capable=False)
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def get_rx_mem_size(self):
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return self.downconn.packet_decoder.mem.depth*self.downconn.packet_decoder.mem.width
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def get_loopback_tx_port(self):
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def get_loopback_tx_port(self):
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return self.downconn.command.mem.get_port(write_capable=True)
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return self.downconn.command.mem.get_port(write_capable=True)
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def get_mem_size(self):
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def get_loopback_tx_mem_size(self):
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return buffer_depth*word_dw
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return self.downconn.command.mem.depth*self.downconn.command.mem.width
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class DownConn_Interface(Module, AutoCSR):
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class DownConn_Interface(Module, AutoCSR):
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def __init__(self, phy, debug_sma, pmod_pads):
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def __init__(self, phy, debug_sma, pmod_pads):
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