forked from M-Labs/artiq-zynq
openocd: remove dead code
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c9b48c80a0
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2c65e6bf6f
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@ -93,119 +93,3 @@ if { $_SMP } {
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-dbgbase 0x80092000
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target smp $_TARGETNAME_0 $_TARGETNAME_1
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}
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#
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# Hack to get the registers into a stable state when first booting a zynq in
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# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
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# register the write will fail because gdb attempts to scan or unwind the
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# current frame and the bad address seems to lock the bus up. This code puts
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# the registers into the OCM and hopefull safe.
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#
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proc zynq_clear_registers { target } {
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echo "Zynq-7000 Series setup: $target"
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set _OCM_END 0x0003FFF0
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mww phys 0xF8007000 0x4E00E07F
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reg r0 0
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reg r1 0
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reg r2 0
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reg r3 0
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reg r4 0
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reg r5 0
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reg r6 0
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reg r7 0
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reg r8 0
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reg r9 0
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reg r10 0
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reg r11 $_OCM_END
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reg sp_svc $_OCM_END
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reg lr_svc $_OCM_END
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reg sp_abt $_OCM_END
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reg lr_abt $_OCM_END
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reg sp_und $_OCM_END
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reg lr_und $_OCM_END
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}
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proc zynq_disable_mmu_and_caches { target } {
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# arm mcr pX op1 CRn CRm op2 value
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echo "Disable MMU and caches"
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# Invalidate caches
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catch {
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$target arm mcr 15 0 7 5 0 0
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$target arm mcr 15 0 7 7 0 0
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# Invalidate all TLBs
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$target arm mcr 15 0 8 5 0 0
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$target arm mcr 15 0 8 6 0 0
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$target arm mcr 15 0 8 7 0 0
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$target arm mcr 15 4 8 3 0 0
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$target arm mcr 15 4 8 7 0 0
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set cp [$target arm mrc 15 0 1 0 0]
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echo "SCTRL => [format 0x%x $cp]"
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set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
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set cp [expr ($cp & ~$mask)]
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$target arm mcr 15 0 1 0 0 $cp
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echo "SCTRL <= [format 0x%x $cp]"
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}
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}
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proc zynq_boot_ocm_setup { } {
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#
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# Enable the OCM
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#
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echo "Zynq Boot OCM setup"
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catch {
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mww phys 0xF8000008 0xDF0D
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mww phys 0xF8000238 0
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mww phys 0xF8000910 0xC
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}
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}
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proc zynq_rtems_setup { } {
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cache_config l2x 0xF8F02000 8
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cortex_a maskisr on
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}
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proc zynq_restart { wait } {
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global _SMP
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global _TARGETNAME_0
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global _TARGETNAME_1
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set target0 $_TARGETNAME_0
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set target1 $_TARGETNAME_1
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echo "Zynq reset, resetting the board ... "
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poll off
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#
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# Issue the reset via the SLCR
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#
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catch {
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mww phys 0xF8000008 0xDF0D
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mww phys 0xF8000200 1
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}
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echo "Zynq reset waiting for $wait msecs ... "
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sleep $wait
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#
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# Reconnect the DAP etc due to the reset.
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#
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$target0 cortex_a dbginit
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$target0 arm core_state arm
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if { $_SMP } {
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$target1 arm core_state arm
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$target1 cortex_a dbginit
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cortex_a smp_off
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}
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poll on
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#
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# We can now halt the core.
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#
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if { $_SMP } {
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targets $target1
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halt
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}
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targets $target0
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halt
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zynq_rtems_setup
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}
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proc zynq_gdb_attach { target } {
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catch {
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halt
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}
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}
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