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cxp downconn fw: doc clean up

This commit is contained in:
morgan 2024-08-02 12:40:16 +08:00
parent 77bff39212
commit 2aef11143a
1 changed files with 5 additions and 19 deletions
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24
src/libboard_artiq/src/cxp_downconn.rs
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@ -27,16 +27,14 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
const K28_5: u8 = 0xBC;
const K28_1: u8 = 0x3C;
const D21_5: u8 = 21 | 5 << 5;
// brute force aligner only align K28_5 on rxdata[:10]
// don't send too much K28_5 in case phase is locked on the wrong stuff
// seems like I need at least 2 K28_5 to work
// NOTE: testing with IDLE word + buildin comma alignment
// NOTE: testing with IDLE word + manual comma alignment
// 62.5MHz OK
// 125MHz OK
// 156.25MHz OK
// 250MHz
// 156.25MHz
// 250MHz OK
// 312.5MHz
// 500MHz ?? havn't change CDR config yet
const LEN: usize = 4;
const DATA: [[u8; LEN]; 2] = [
// [K28_5, K28_1, K28_5, K28_1],
@ -45,13 +43,6 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
[1, 1, 1, 0],
];
// // STEP 1: reset QPLL
// csr::cxp::downconn_qpll_reset_write(1);
// info!("waiting for QPLL/CPLL to lock...");
// while csr::cxp::downconn_qpll_locked_read() != 1 {}
// info!("QPLL locked");
// STEP 2: setup tx/rx gtx
csr::cxp::downconn_data_0_write(DATA[0][0]);
csr::cxp::downconn_data_1_write(DATA[0][1]);
csr::cxp::downconn_data_2_write(DATA[0][2]);
@ -62,12 +53,7 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
csr::cxp::downconn_control_bit_2_write(DATA[1][2]);
csr::cxp::downconn_control_bit_3_write(DATA[1][3]);
// TEST: change rx linerate
// works great
// enable cxp gtx clock domains
info!("waiting for tx setup...");
info!("waiting for tx&rx setup...");
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",