forked from M-Labs/artiq-zynq
pipeline GW: fix long synth bug
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8260387a99
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@ -250,7 +250,7 @@ class TX_Test_Packet(Module, AutoCSR):
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self.source = stream.Endpoint(word_layout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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cnt = Signal(0xFFF)
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cnt = Signal(max=0xFFF)
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fsm.act("IDLE",
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NextValue(cnt, cnt.reset),
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If(self.tx.re,
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