forked from M-Labs/artiq-zynq
work around boot.bin/fsbl problems
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE). * Prevent boot.bin creation tool from crashing due to long paths.
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parent
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commit
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19
default.nix
19
default.nix
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@ -96,17 +96,24 @@ in
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buildInputs = [ mkbootimage ];
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buildInputs = [ mkbootimage ];
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}
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}
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''
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''
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bif=`mktemp`
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# Do not use "long" paths in boot.bif, because embedded developers
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cat > $bif << EOF
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# can't write software (mkbootimage will segfault).
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# TODO: use self-built fsbl
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bifdir=`mktemp -d`
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cd $bifdir
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ln -s ${./fsbl.elf} fsbl.elf
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ln -s ${zc706-gateware}/top.bit top.bit
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ln -s ${zc706-firmware}/runtime.elf runtime.elf
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cat > boot.bif << EOF
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the_ROM_image:
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the_ROM_image:
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{
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{
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[bootloader]${zc706-fsbl}/fsbl.elf
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[bootloader]fsbl.elf
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${zc706-gateware}/top.bit
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top.bit
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${zc706-firmware}/runtime.elf
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runtime.elf
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}
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}
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EOF
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EOF
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mkdir $out $out/nix-support
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mkdir $out $out/nix-support
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mkbootimage $bif $out/boot.bin
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mkbootimage boot.bif $out/boot.bin
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echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
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echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
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'';
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'';
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}
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}
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