morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

pipeline GW: rename modules

Browse Source
This commit is contained in:
morgan 2025-01-14 14:54:30 +08:00
parent 09d2ccf99f
commit 271cbd8e49
1 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/gateware/cxp_pipeline.py
View File

@ -79,7 +79,7 @@ class Packet_Wrapper(Module):
If(self.source.ack, NextState("IDLE")),
)
class TX_Trigger(Module):
class Trigger_Inserter(Module):
def __init__(self):
self.stb = Signal()
self.delay = Signal(char_width)
@ -201,13 +201,13 @@ class Trigger_ACK_Inserter(Module):
@FullMemoryWE()
class TX_Bootstrap(Module, AutoCSR):
class Control_Packet_Writer(Module, AutoCSR):
def __init__(self):
self.tx_word_len = CSRStorage(log2_int(buffer_depth))
self.tx = CSR()
self.tx_testseq = CSR()
self.word_len = Signal(log2_int(buffer_depth))
self.stb = Signal()
self.stb_testseq = Signal()
self.tx_busy = CSRStatus()
self.busy = Signal()
# # #
@ -234,13 +234,13 @@ class TX_Bootstrap(Module, AutoCSR):
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
cnt = Signal(max=0xFFF)
fsm.act("IDLE",
addr_rst.eq(1),
If(self.tx.re, NextState("TRANSMIT")),
If(self.tx_testseq.re,
If(self.stb, NextState("TRANSMIT")),
If(self.stb_testseq,
NextValue(cnt, cnt.reset),
NextState("WRITE_TEST_PACKET_TYPE"),
)
@ -252,7 +252,7 @@ class TX_Bootstrap(Module, AutoCSR):
If(self.source.ack,
addr_inc.eq(1),
),
If(addr_next == self.tx_word_len.storage,
If(addr_next == self.word_len,
self.source.eop.eq(1),
NextState("IDLE")
)
@ -365,7 +365,7 @@ class Duplicated_Char_Decoder(Module):
@FullMemoryWE()
class RX_Bootstrap(Module):
class Control_Packet_Reader(Module):
def __init__(self):
self.packet_type = Signal(8)