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frameline GW: remove eop marker

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This commit is contained in:
morgan 2025-01-14 10:46:01 +08:00
parent 7ea3d563e6
commit 26d940fbc3
1 changed files with 7 additions and 55 deletions
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62
src/gateware/cxp_frame_pipeline.py
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@ -21,27 +21,6 @@ def switch_endianness(s):
char = [s[i*8:(i+1)*8] for i in range(len(s)//8)] char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
return Cat(char[::-1]) return Cat(char[::-1])
class EOP_Inserter(Module):
def __init__(self):
self.sink = stream.Endpoint(word_layout_dchar)
self.source = stream.Endpoint(word_layout_dchar)
# # #
self.sync += [
If((~self.source.stb | self.source.ack),
If(~((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
self.sink.connect(self.source, omit={"ack", "eop"}),
).Else(
self.source.stb.eq(0),
)
),
]
self.comb += [
self.sink.ack.eq(~self.source.stb | self.source.ack),
self.source.eop.eq(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1))),
]
class End_Of_Line_Inserter(Module): class End_Of_Line_Inserter(Module):
def __init__(self): def __init__(self):
self.l_size = Signal(3*char_width) self.l_size = Signal(3*char_width)
@ -76,26 +55,6 @@ class End_Of_Line_Inserter(Module):
self.source.eop.eq(cnt == 1), self.source.eop.eq(cnt == 1),
] ]
class EOP_Marker(Module):
def __init__(self):
self.sink = stream.Endpoint(word_layout_dchar)
self.source = stream.Endpoint(word_layout_dchar)
# # #
last_stb = Signal()
self.sync += [
If((~self.source.stb | self.source.ack),
self.source.stb.eq(self.sink.stb),
self.source.payload.eq(self.sink.payload),
),
last_stb.eq(self.sink.stb),
]
self.comb += [
self.sink.ack.eq(~self.source.stb | self.source.ack),
self.source.eop.eq(~self.sink.stb & last_stb),
]
class Stream_Arbiter(Module): class Stream_Arbiter(Module):
def __init__(self, n_downconn): def __init__(self, n_downconn):
self.n_ext_active = Signal(max=n_downconn) self.n_ext_active = Signal(max=n_downconn)
@ -657,11 +616,11 @@ class Frame_Packet_Router(Module):
# # # # # #
# +----------+ +-------------+ # +---------+ +-------------+
# eop marker ----->| | | |------> crc checker # rx pipline ----->| | | |------> crc checker ------> raw stream data
# | arbiter |---->| broadcaster | # | arbiter |---->| broadcaster |
# eop marker ----->| need eop | | |------> crc checker # rx pipline ----->| | | |------> crc checker ------> raw stream data
# +----------+ +-------------+ # +---------+ +-------------+
# #
self.submodules.arbiter = arbiter = Stream_Arbiter(n_downconn) self.submodules.arbiter = arbiter = Stream_Arbiter(n_downconn)
@ -672,15 +631,8 @@ class Frame_Packet_Router(Module):
self.sync += broadcaster.routing_table[i].eq(s) self.sync += broadcaster.routing_table[i].eq(s)
for i, d in enumerate(downconns): for i, d in enumerate(downconns):
# eop is needed for arbiter and crc checker to work correctly # Assume downconns pipeline already marks the eop
# TODO: move eop inserter inside of broadcaster self.comb += d.source.connect(arbiter.sinks[i])
# TODO: change arbiter to use K27.7 as eop instead
eop_marker = EOP_Inserter()
self.submodules += eop_marker
self.comb += [
d.source.connect(eop_marker.sink),
eop_marker.source.connect(arbiter.sinks[i])
]
self.comb += arbiter.source.connect(broadcaster.sink) self.comb += arbiter.source.connect(broadcaster.sink)