forked from M-Labs/artiq-zynq
libboard_artiq: setup
libboard_artiq: add cxp_downconn & cxp_upconn libboard_artiq: compile mem with cxp libboard_artiq: add cxp_proto libboard_artiq: add cxp_phys
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@ -26,7 +26,7 @@ pub mod fiq;
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#[cfg(feature = "target_kasli_soc")]
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#[cfg(feature = "target_kasli_soc")]
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pub mod io_expander;
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pub mod io_expander;
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pub mod logger;
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pub mod logger;
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#[cfg(has_drtio)]
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#[cfg(any(has_drtio, has_cxp_phys))]
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#[rustfmt::skip]
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#[rustfmt::skip]
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#[path = "../../../build/mem.rs"]
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#[path = "../../../build/mem.rs"]
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pub mod mem;
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pub mod mem;
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@ -43,6 +43,15 @@ pub mod si5324;
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pub mod si549;
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pub mod si549;
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use core::{cmp, str};
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use core::{cmp, str};
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#[cfg(has_cxp_phys)]
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pub mod cxp_downconn;
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#[cfg(has_cxp_phys)]
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pub mod cxp_upconn;
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pub mod cxp_proto;
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pub mod cxp_phys;
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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pub fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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unsafe {
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pl::csr::identifier::address_write(0);
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pl::csr::identifier::address_write(0);
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