forked from M-Labs/artiq-zynq
zc706 GW: use mem region getter
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2ca9a3191d
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256f2f7e8c
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@ -719,24 +719,25 @@ class CXP_FMC():
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cxp_csr_group.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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mem_size = cxp_interface .get_mem_size()
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tx_mem_name = "cxp_tx" + str(i) + "_mem"
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tx_mem_name = "cxp_tx" + str(i) + "_mem"
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memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
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tx_mem_size = cxp_interface.get_tx_mem_size()
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self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
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memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size)
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self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size)
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cxp_tx_mem_group.append(tx_mem_name)
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cxp_tx_mem_group.append(tx_mem_name)
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rx_mem_name = "cxp_rx" + str(i) + "_mem"
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rx_mem_name = "cxp_rx" + str(i) + "_mem"
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memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
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rx_mem_size = cxp_interface.get_rx_mem_size()
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self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
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memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
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self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
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cxp_rx_mem_group.append(rx_mem_name)
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cxp_rx_mem_group.append(rx_mem_name)
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# DEBUG loopback tx memory
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# DEBUG loopback tx memory
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loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
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loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
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loopback_mem_size = cxp_interface.get_loopback_tx_mem_size()
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cxp_loopback_mem_group.append(loopback_mem_name)
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cxp_loopback_mem_group.append(loopback_mem_name)
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memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), mem_size)
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memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), loopback_mem_size)
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self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, mem_size)
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self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, loopback_mem_size)
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self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
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self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
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self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
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self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
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