From 24a1f27705ad98cc8ebe2f79f4883adc52f202a5 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Mon, 7 Oct 2024 13:15:18 +0800
Subject: [PATCH] pipeline GW: add ring buffer

---
 src/gateware/cxp_pipeline.py | 45 ++++++++++++++++++++++++++----------
 1 file changed, 33 insertions(+), 12 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index d1c02a6..192c5f6 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -1,4 +1,5 @@
 from migen import *
+from migen.genlib.cdc import MultiReg 
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCChecker
@@ -8,6 +9,8 @@ char_layout = [("data", char_width), ("k", char_width//8)]
 
 word_dw = 32
 word_layout = [("data", word_dw), ("k", word_dw//8)]
+
+buffer_count = 4
 buffer_depth = 128
 
 def K(x, y):
@@ -302,9 +305,6 @@ class RX_Debug_Buffer(Module,AutoCSR):
 class CXP_Data_Packet_Decode(Module):
     def __init__(self):
         self.packet_type = Signal(8)
-        self.write_ptr = Signal(bits_for(buffer_depth))
-
-        self.new_packet = Signal()
         self.decode_err = Signal()
         self.test_err = Signal()
         # # #
@@ -338,23 +338,35 @@ class CXP_Data_Packet_Decode(Module):
         )
 
         cnt = Signal(max=0x100)
+        addr_nbits = log2_int(buffer_depth)
+        addr = Signal(addr_nbits)
         fsm.act("DECODE",
             self.sink.ack.eq(1),
             If(self.sink.stb,
-                self.new_packet.eq(1),
                 NextValue(self.packet_type, self.sink.data[:8]),
 
                 Case(self.sink.data[:8],{
                     type["data_stream"]: NextState("STREAMING"),
-                    type["control_ack_no_tag"]: NextState("LOAD_BUFFER"),
+                    type["control_ack_no_tag"]:[
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
                     type["test_packet"]: [
                         NextValue(cnt, cnt.reset),
                         NextState("VERIFY_TEST_PATTERN"),
                     ],
-                    type["control_ack_with_tag"]: NextState("LOAD_BUFFER"),
-                    type["event"]: NextState("LOAD_BUFFER"),
-
-                    type["debug"]: NextState("LOAD_BUFFER"),
+                    type["control_ack_with_tag"]:[
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["event"]: [
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["debug"]: [
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
                     "default": [
                          self.decode_err.eq(1),
                          # wait till next valid packet
@@ -398,10 +410,18 @@ class CXP_Data_Packet_Decode(Module):
         )
 
         # A circular buffer for firmware to read packet from
-        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.specials.mem = mem = Memory(word_dw, buffer_count*buffer_depth)
         self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
 
-        self.comb += mem_port.adr.eq(self.write_ptr),
+        write_ptr = Signal(log2_int(buffer_count))
+        self.write_ptr_sys = Signal.like(write_ptr)
+        self.specials += MultiReg(write_ptr, self.write_ptr_sys),
+
+        self.comb += [
+            mem_port.adr[:addr_nbits].eq(addr),
+            mem_port.adr[addr_nbits:].eq(write_ptr),
+        ]
+
 
         # For control ack, event packet
         fsm.act("LOAD_BUFFER",
@@ -409,11 +429,12 @@ class CXP_Data_Packet_Decode(Module):
             self.sink.ack.eq(1),
             If(self.sink.stb,
                 If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+                    NextValue(write_ptr, write_ptr + 1),
                     NextState("IDLE"),
                 ).Else(
                     mem_port.we.eq(1),
                     mem_port.dat_w.eq(self.sink.data),
-                    NextValue(self.write_ptr, self.write_ptr + 1),
+                    NextValue(addr, addr + 1),
                 )
             )
         )