forked from M-Labs/artiq-zynq
frameline GW: move err cnt out & improve timing
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56b1553bdb
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@ -122,7 +122,8 @@ class CXPCRC32(Module):
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class CXPCRC32_Checker(Module):
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class CXPCRC32_Checker(Module):
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"""Verify crc in stream data packet"""
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"""Verify crc in stream data packet"""
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def __init__(self):
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def __init__(self):
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self.error_cnt = Signal(16)
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# TODO: handle the error into a counter
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self.error = Signal()
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self.sink = stream.Endpoint(word_layout_dchar)
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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@ -140,7 +141,7 @@ class CXPCRC32_Checker(Module):
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fsm.act("RESET",
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fsm.act("RESET",
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crc.reset.eq(1),
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crc.reset.eq(1),
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If(crc.error, NextValue(self.error_cnt, self.error_cnt + 1)),
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self.error.eq(crc.error),
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NextState("CHECKING"),
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NextState("CHECKING"),
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)
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)
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