diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index 2c370cb..2a6f89a 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -180,11 +180,8 @@ class Packets_Scheduler(Module):
 class TxFIFOs(Module):
     def __init__(self, cxp_phy_layout, nfifos, fifo_depth):
 
-        self.sink_full = Signal(nfifos) 
-        self.sink_stb = Signal(nfifos)
-        self.sink_data = [Signal(8) for _ in range(nfifos)]
-        self.sink_k = [Signal() for _ in range(nfifos)]
-        
+        self.sink = []
+
         self.source_ack = Array(Signal() for _ in range(nfifos))
         self.source_data = Array(Signal(8) for _ in range(nfifos))
         self.source_k = Array(Signal() for _ in range(nfifos))
@@ -195,17 +192,14 @@ class TxFIFOs(Module):
 
         for i in range(nfifos):
             fifo = stream.SyncFIFO(cxp_phy_layout, fifo_depth)
-
             setattr(self.submodules, "tx_fifo" + str(i), fifo)
 
-            self.sync += [
-                fifo.sink.stb.eq(self.sink_stb[i]),
-                self.sink_full[i].eq(fifo.sink.ack),
-                fifo.sink.data.eq(self.sink_data[i]),
-                fifo.sink.k.eq(self.sink_k[i]),
+            self.sink += [fifo.sink]
 
+            self.sync += [
                 If(self.source_ack[i], 
                     # reset ack after asserted 
+                    # since upconn clk run much slower, the ack will be high for longer than expected which will result in data loss
                     self.source_ack[i].eq(0),
                     fifo.source.ack.eq(1),
                 ).Else(