morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp downconn: explore cpll & txusrclk_pll divider

This commit is contained in:
morgan 2024-07-25 17:39:11 +08:00
parent 6c53447808
commit 20e388d043
1 changed files with 16 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/gateware/cxp_downconn.py
View File

@ -130,8 +130,15 @@ class CXP_DownConn(Module):
assert tx_mode in ["single", "master", "slave"] assert tx_mode in ["single", "master", "slave"]
assert rx_mode in ["single", "master", "slave"] assert rx_mode in ["single", "master", "slave"]
cpll_div = 4 cpll_div = 5
pll_div = int(40/cpll_div) cpll_div45 = 5
refclk_div = 1
Xxout_div = 2
# linerate = sys * cpll_mult
cpll_mult = 2 * cpll_div * cpll_div45 / (Xxout_div * refclk_div)
pll_fbout_mult = 10
txusr_pll_div = pll_fbout_mult*20/cpll_mult # 20 is datawidth
self.rx_restart = Signal() self.rx_restart = Signal()
self.tx_restart = Signal() self.tx_restart = Signal()
@ -185,10 +192,10 @@ class CXP_DownConn(Module):
# CPLL # CPLL
p_CPLL_CFG=0xBC07DC, p_CPLL_CFG=0xBC07DC,
p_CPLL_FBDIV=cpll_div, p_CPLL_FBDIV=cpll_div,
p_CPLL_FBDIV_45=5, p_CPLL_FBDIV_45=cpll_div45,
p_CPLL_REFCLK_DIV=1, p_CPLL_REFCLK_DIV=refclk_div,
p_RXOUT_DIV=2, p_RXOUT_DIV=Xxout_div,
p_TXOUT_DIV=2, p_TXOUT_DIV=Xxout_div,
p_CPLL_INIT_CFG=0x00001E, p_CPLL_INIT_CFG=0x00001E,
p_CPLL_LOCK_CFG=0x01E8, p_CPLL_LOCK_CFG=0x01E8,
i_CPLLRESET=cpllreset, i_CPLLRESET=cpllreset,
@ -388,11 +395,11 @@ class CXP_DownConn(Module):
i_CLKIN1=txoutclk_buf, i_CLKIN1=txoutclk_buf,
# VCO @ 1.25GHz # VCO @ 1.25GHz
p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk, i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk,
# 156.25MHz # frequency = linerate/20
p_CLKOUT0_DIVIDE=pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout, p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
# TODO: DRP for line rate change # TODO: DRP for line rate change
), ),