forked from M-Labs/artiq-zynq
cxp upconn: add low speed serial
cxp upconn: add low speed serial cxp upconn: add pll for bitrate2x mode cxp upconn: add tx_fifos & idle with encoder cxp upconn: add priority packet that send in word/char boundary
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7d5e3c1ef9
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1f033d605c
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.coding import PriorityEncoder
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from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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class CXP_UpConn(Module, AutoCSR):
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nfifos = 3
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def __init__(self, pads, sys_clk_freq, pmod, fifo_depth=32):
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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self.tx_enable = CSRStorage()
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# # #
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pll_locked = Signal()
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pll_fb_clk = Signal()
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pll_cxpclk = Signal()
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pll_cxpclk2x = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_BANDWIDTH="HIGH",
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o_LOCKED=pll_locked,
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i_RST=ResetSignal("sys"),
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p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
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i_CLKIN1=ClockSignal("sys"),
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# VCO @ 1.25GHz
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p_CLKFBOUT_MULT=1.25e9/sys_clk_freq, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=pll_fb_clk, o_CLKFBOUT=pll_fb_clk,
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# 20.83MHz (48ns)
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p_CLKOUT0_DIVIDE=60, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_cxpclk,
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# 41.66MHz (24ns) for downconnection over 6.25Gpbs
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p_CLKOUT1_DIVIDE=30, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_cxpclk2x,
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),
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Instance("BUFGMUX",
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i_I0=pll_cxpclk,
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i_I1=pll_cxpclk2x,
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i_S=self.bitrate2x_enable.storage,
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o_O=self.cd_cxp_upconn.clk
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),
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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]
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self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.tx_fifos = TxFIFOs(self.nfifos, fifo_depth)
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self.submodules.tx_idle = TxIdle()
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o = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_wordcount = Signal(max=4)
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tx_reg = Signal(10)
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disp = Signal()
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priorities = Signal(max=self.nfifos)
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idling = Signal()
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# startup sequence
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self.fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable.storage,
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NextValue(self.tx_idle.word_idx, 0),
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NextValue(tx_wordcount, 0),
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NextValue(tx_bitcount, 0),
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NextState("LOAD_CHAR")
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)
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)
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self.fsm.act("LOAD_CHAR",
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NextValue(idling, 1),
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NextValue(self.tx_idle.source_ack, 1),
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NextValue(tx_reg, self.tx_idle.source_data),
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NextValue(disp, self.tx_idle.disp_out),
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NextState("START_TX")
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)
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self.fsm.act("START_TX",
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tx_en.eq(1),
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If((~self.tx_enable.storage) & (tx_wordcount == 3),
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NextState("WAIT_TX_ENABLE")
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)
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)
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self.sync.cxp_upconn += [
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self.tx_fifos.disp_in.eq(disp),
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self.tx_idle.disp_in.eq(disp),
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If(tx_en,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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# char boundary
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If(tx_bitcount == 9,
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tx_bitcount.eq(0),
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If((~self.tx_fifos.pe.n) & (self.tx_fifos.pe.o == 0),
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# trigger packets are inserted at char boundary and don't contribute to word count
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tx_reg.eq(self.tx_fifos.source_data[0]),
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self.tx_fifos.source_ack[0].eq(1),
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disp.eq(self.tx_fifos.disp_out[0]),
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).Else(
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# word boundary
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If(tx_wordcount == 3,
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tx_wordcount.eq(0),
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If(~self.tx_fifos.pe.n,
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# priority lv 1 & 2 packets are inserted at word boundary
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idling.eq(0),
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priorities.eq(self.tx_fifos.pe.o),
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self.tx_fifos.source_ack[self.tx_fifos.pe.o].eq(1),
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tx_reg.eq(self.tx_fifos.source_data[self.tx_fifos.pe.o]),
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disp.eq(self.tx_fifos.disp_out[self.tx_fifos.pe.o]),
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).Else(
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idling.eq(1),
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self.tx_idle.source_ack.eq(1),
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tx_reg.eq(self.tx_idle.source_data),
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disp.eq(self.tx_idle.disp_out),
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)
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).Else(
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tx_wordcount.eq(tx_wordcount + 1),
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If(~idling,
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self.tx_fifos.source_ack[priorities].eq(1),
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tx_reg.eq(self.tx_fifos.source_data[priorities]),
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disp.eq(self.tx_fifos.disp_out[priorities]),
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).Else(
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self.tx_idle.source_ack.eq(1),
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tx_reg.eq(self.tx_idle.source_data),
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disp.eq(self.tx_idle.disp_out),
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)
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),
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)
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)
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).Else(
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o.eq(0)
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)
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]
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# DEBUG: remove pads
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self.encoded_data = CSRStatus(10)
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self.sync.cxp_upconn +=[
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If(tx_bitcount == 0,
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self.encoded_data.status.eq(tx_reg),
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)
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]
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ninth_bit = Signal()
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word_bound = Signal()
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p0 = Signal()
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p3 = Signal()
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self.comb += [
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ninth_bit.eq(tx_bitcount == 9),
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word_bound.eq(tx_wordcount == 3),
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p0.eq(self.tx_idle.word_idx == 0),
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p3.eq(self.tx_idle.word_idx == 3),
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]
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self.specials += [
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# debug sma
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Instance("OBUF", i_I=o, o_O=pads.p_tx),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx),
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# pmod 0-7 pin
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Instance("OBUF", i_I=o, o_O=pmod[0]),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
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Instance("OBUF", i_I=~self.tx_fifos.pe.n, o_O=pmod[2]),
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Instance("OBUF", i_I=ninth_bit, o_O=pmod[3]),
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Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
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Instance("OBUF", i_I=idling, o_O=pmod[5]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]),
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Instance("OBUF", i_I=p0, o_O=pmod[6]),
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Instance("OBUF", i_I=p3, o_O=pmod[7]),
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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self.symbol2 = CSR(9)
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self.sync += [
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self.tx_fifos.sink_stb[0].eq(self.symbol0.re),
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self.tx_fifos.sink_data[0].eq(self.symbol0.r),
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self.tx_fifos.sink_stb[1].eq(self.symbol1.re),
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self.tx_fifos.sink_data[1].eq(self.symbol1.r),
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self.tx_fifos.sink_stb[2].eq(self.symbol2.re),
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self.tx_fifos.sink_data[2].eq(self.symbol2.r),
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]
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class TxFIFOs(Module):
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def __init__(self, nfifos, fifo_depth):
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self.disp_in = Signal()
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self.disp_out = Array(Signal() for _ in range(nfifos))
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self.sink_stb = Signal(nfifos)
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self.sink_ack = Signal(nfifos)
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self.sink_data = [Signal(9) for _ in range(nfifos)]
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self.source_ack = Array(Signal() for _ in range(nfifos))
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self.source_data = Array(Signal(10) for _ in range(nfifos))
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# # #
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source_stb = Signal(nfifos)
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for i in range(nfifos):
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
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encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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setattr(self.submodules, "tx_fifo" + str(i), fifo)
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setattr(self.submodules, "tx_encoder" + str(i), encoder)
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self.sync += [
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fifo.sink.stb.eq(self.sink_stb[i]),
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self.sink_ack[i].eq(fifo.sink.ack),
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fifo.sink.data.eq(self.sink_data[i]),
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]
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self.sync.cxp_upconn += [
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encoder.d.eq(fifo.source.data[:8]),
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encoder.k.eq(fifo.source.data[8]),
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encoder.disp_in.eq(self.disp_in),
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self.disp_out[i].eq(encoder.disp_out),
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source_stb[i].eq(fifo.source.stb),
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fifo.source.ack.eq(self.source_ack[i]),
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self.source_data[i].eq(encoder.output),
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# reset ack after asserted
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If(self.source_ack[i], self.source_ack[i].eq(0)),
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]
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# FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(source_stb)
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class TxIdle(Module):
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def __init__(self):
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self.disp_in = Signal()
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self.disp_out = Signal()
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self.word_idx = Signal(max=4)
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self.source_ack = Signal()
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self.source_data = Signal(10)
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# # #
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# CXP 2.1 section 9.2.5
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IDLE_CHARS = Array([
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#[char, k]
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[0b10111100, 1], #K28.5
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[0b00111100, 1], #K28.1
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[0b00111100, 1], #K28.1
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[0b10111100, 0], #D28.5
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])
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encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.submodules += encoder
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self.sync.cxp_upconn += [
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encoder.d.eq(IDLE_CHARS[self.word_idx][0]),
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encoder.k.eq(IDLE_CHARS[self.word_idx][1]),
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encoder.disp_in.eq(self.disp_in),
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self.disp_out.eq(encoder.disp_out),
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self.source_data.eq(encoder.output),
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If(self.source_ack,
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# reset after asserted
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self.source_ack.eq(0),
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If(self.word_idx != 3,
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self.word_idx.eq(self.word_idx + 1),
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).Else(
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self.word_idx.eq(0),
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)
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),
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]
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