forked from M-Labs/artiq-zynq
cxp: remove all cxp downconn interface
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@ -2,148 +2,20 @@ from migen import *
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from misoc.interconnect.csr import *
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from artiq.gateware.drtio.core import ChannelInterface
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from cxp_downconn import CXP_DownConn
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from cxp_upconn import CXP_UpConn
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class CXP(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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nchannels = len(pads)
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self.rx_start_init = CSRStorage()
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self.rx_restart = CSRStorage()
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self.rx_data_alignment = CSRStorage()
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self.tx_start_init = CSRStorage()
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self.tx_restart = CSRStorage()
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self.loopback_mode = CSRStorage(3)
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self.txinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.rx_ready = CSRStatus()
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self.data_0 = CSRStorage(8)
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self.data_1 = CSRStorage(8)
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self.data_2 = CSRStorage(8)
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self.data_3 = CSRStorage(8)
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self.control_bit_0 = CSRStorage()
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self.control_bit_1 = CSRStorage()
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self.control_bit_2 = CSRStorage()
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self.control_bit_3 = CSRStorage()
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self.encoded_0 = CSRStatus(10)
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self.encoded_1 = CSRStatus(10)
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self.rxdata_0 = CSRStatus(10)
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self.rxdata_1 = CSRStatus(10)
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self.decoded_data_0 = CSRStatus(8)
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self.decoded_data_1 = CSRStatus(8)
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self.decoded_k_0 = CSRStatus()
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self.decoded_k_1 = CSRStatus()
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# # #
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self.submodules.crc = CXP_CRC(8)
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# FIFOs with transmission priority
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# 0: Trigger packet
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# 1: IO acknowledgment for trigger packet
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# 2: All other packets
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self.submodules.upconn = CXP_UpConn(debug_sma, sys_clk_freq, pmod_pads)
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self.submodules.downconn = CXP_DownConn(refclk, pads, sys_clk_freq, debug_sma, pmod_pads)
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# single & master tx_mode can lock with rx in loopback
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self.submodules.gtx = gtx = CXP_DownConn(refclk, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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# DEBUG:loopback
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self.sync += gtx.loopback_mode.eq(self.loopback_mode.storage)
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# DEBUG:SMA
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self.specials += [
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Instance("OBUF", i_I=gtx.rxoutclk, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=gtx.cd_cxp_gtx_tx.clk, o_O=debug_sma.n_rx)
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]
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self.comb += [
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self.txinit_phaligndone.status.eq(self.gtx.tx_init.Xxphaligndone),
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# self.rxinit_phaligndone.status.eq(self.gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(self.gtx.rx_ready),
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]
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counter_max = 4
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counter = Signal(max=counter_max)
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self.sync.cxp_gtx_tx += [
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If(counter == 0,
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self.gtx.encoder.d[0].eq(self.data_0.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_0.storage),
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self.gtx.encoder.d[1].eq(self.data_1.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_1.storage),
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counter.eq(counter+1),
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).Elif(counter == 1,
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self.gtx.encoder.d[0].eq(self.data_2.storage),
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self.gtx.encoder.k[0].eq(self.control_bit_2.storage),
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self.gtx.encoder.d[1].eq(self.data_3.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
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counter.eq(0),
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),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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]
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self.sync.cxp_gtx_rx += [
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self.rxdata_0.status.eq(self.gtx.decoders[0].input),
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self.decoded_data_0.status.eq(self.gtx.decoders[0].d),
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self.decoded_k_0.status.eq(self.gtx.decoders[0].k),
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self.rxdata_1.status.eq(self.gtx.decoders[1].input),
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self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
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self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
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]
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# TODO: rip encoder & rx clockalignment out of CXP_GTX
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# TODO: use expose encoder & decoder from CXP
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# encoder.k = 1 if sending control bit, different calculation
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# encoder.d = data 8 bit
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channel_interface = ChannelInterface(gtx.encoder, gtx.decoders)
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self.comb += channel_interface.rx_ready.eq(gtx.rx_ready)
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channel_interfaces = []
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channel_interfaces.append(channel_interface)
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# TransceiverInterface, just adding cxp_rx_<num>
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self.stable_clkin = CSRStorage()
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self.txenable = CSRStorage(len(channel_interfaces))
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for i in range(len(channel_interfaces)):
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name = "cxp_gtx_rx" + str(i)
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setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
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self.channels = channel_interfaces
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# TODO: add tx_phase_alignment for multi CXP
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# The TX phase alignment will fail with a wrong TXUSRCLK frequency
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self.comb += [
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.storage),
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gtx.rx_restart.eq(self.rx_restart.storage),
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gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
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gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
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gtx.rx_alignment_en.eq(self.rx_data_alignment.storage),
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]
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# TODO: Connect multilane cxp_tx
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# TODO: Connect slave i's `cxp_gtx_rx` clock to `cxp_gtx_rxi` clock
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self.comb += [
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getattr(self, "cd_cxp_gtx_rx" + str(0)).clk.eq(self.gtx.cd_cxp_gtx_rx.clk),
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getattr(self, "cd_cxp_gtx_rx" + str(0)).rst.eq(self.gtx.cd_cxp_gtx_rx.rst)
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]
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class CXP_CRC(Module, AutoCSR):
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width = 32
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