forked from M-Labs/artiq-zynq
zc706 master: route sma clock to si5324
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3cf86a6335
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1d731a3589
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@ -71,6 +71,19 @@ class RTIOCRG(Module, AutoCSR):
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]
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]
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("user_sma_clock")
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sma_clkin_se = Signal()
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si5324_clkin_se = Signal()
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += [
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=si5324_clkin_se),
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Instance("OBUFDS", i_I=si5324_clkin_se, o_O=si5324_clkin.p, o_OB=si5324_clkin.n)
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]
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
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# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
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# This also changes the I/O standard for some on-board LEDs.
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# This also changes the I/O standard for some on-board LEDs.
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leds_fmc33 = [
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leds_fmc33 = [
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@ -205,6 +218,8 @@ class _MasterBase(SoCCore):
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platform.request("user_sma_mgt")
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platform.request("user_sma_mgt")
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]
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]
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self.submodules += SMAClkinForward(self.platform)
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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self.submodules.drtio_transceiver = gtx_7series.GTX(
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clock_pads=platform.request("si5324_clkout"),
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clock_pads=platform.request("si5324_clkout"),
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