morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

downconn GW: general cleanup

This commit is contained in:
morgan 2024-09-16 12:57:14 +08:00
parent 9ecc3cebb6
commit 1b704a738c
1 changed files with 6 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/gateware/cxp_downconn.py
View File

@ -103,17 +103,12 @@ class CXP_DownConn_PHY(Module, AutoCSR):
self.sources = []
for n, gtx in enumerate(self.gtxs):
# DEBUG: remove cdc fifo
# gtx rx -> fifo out -> cdc out
fifo_out = stream.SyncFIFO(downconn_layout, 128)
self.submodules += ClockDomainsRenamer("cxp_gtx_rx")(fifo_out)
cdc_out = stream.AsyncFIFO(downconn_layout, 128)
self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_out)
self.sources.append(cdc_out)
self.comb += fifo_out.source.connect(cdc_out.sink)
fifo_out = stream.AsyncFIFO(downconn_layout, 128)
self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
self.sources.append(fifo_out)
for i in range(4):
self.sync.cxp_gtx_rx += [
@ -168,7 +163,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage)
# DEBUG: datain
# fw -> fifo (sys) -> cdc fifo -> fifo in -> gtx tx
# fw -> fifo (sys) -> cdc fifo -> gtx tx
fifo_in = stream.AsyncFIFO(downconn_layout, 128)
self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
@ -185,6 +180,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
)
]
# NOTE: prevent the first word send twice due to stream stb delay
self.comb += [
If(fifo_in.source.stb & fifo_in.source.ack,
gtx.encoder.d[0].eq(fifo_in.source.data[:8]),