diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index aceeea1..b7aa08a 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -103,17 +103,12 @@ class CXP_DownConn_PHY(Module, AutoCSR):
         self.sources = []
         
         for n, gtx in enumerate(self.gtxs):
-
+            # DEBUG: remove cdc fifo
             # gtx rx -> fifo out -> cdc out
             
-            fifo_out = stream.SyncFIFO(downconn_layout, 128)
-            self.submodules += ClockDomainsRenamer("cxp_gtx_rx")(fifo_out)
-
-            cdc_out = stream.AsyncFIFO(downconn_layout, 128)
-            self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_out)
-            self.sources.append(cdc_out)
-            self.comb += fifo_out.source.connect(cdc_out.sink)
-
+            fifo_out = stream.AsyncFIFO(downconn_layout, 128)
+            self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(fifo_out)
+            self.sources.append(fifo_out)
 
             for i in range(4):
                 self.sync.cxp_gtx_rx += [
@@ -168,7 +163,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
             self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage) 
 
             # DEBUG: datain
-            # fw -> fifo (sys) -> cdc fifo -> fifo in -> gtx tx
+            # fw -> fifo (sys) -> cdc fifo -> gtx tx
             
             fifo_in = stream.AsyncFIFO(downconn_layout, 128)
             self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(fifo_in)
@@ -185,6 +180,7 @@ class CXP_DownConn_PHY(Module, AutoCSR):
                 )
             ]
 
+            # NOTE: prevent the first word send twice due to stream stb delay 
             self.comb += [
                 If(fifo_in.source.stb & fifo_in.source.ack,
                     gtx.encoder.d[0].eq(fifo_in.source.data[:8]),