forked from M-Labs/artiq-zynq
cxp: remove data[4:8]
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398eb135c7
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@ -27,18 +27,10 @@ class CXP(Module, AutoCSR):
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self.data_1 = CSRStorage(8)
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self.data_1 = CSRStorage(8)
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self.data_2 = CSRStorage(8)
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self.data_2 = CSRStorage(8)
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self.data_3 = CSRStorage(8)
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self.data_3 = CSRStorage(8)
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self.data_4 = CSRStorage(8)
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self.data_5 = CSRStorage(8)
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self.data_6 = CSRStorage(8)
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self.data_7 = CSRStorage(8)
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self.control_bit_0 = CSRStorage()
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self.control_bit_0 = CSRStorage()
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self.control_bit_1 = CSRStorage()
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self.control_bit_1 = CSRStorage()
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self.control_bit_2 = CSRStorage()
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self.control_bit_2 = CSRStorage()
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self.control_bit_3 = CSRStorage()
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self.control_bit_3 = CSRStorage()
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self.control_bit_4 = CSRStorage()
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self.control_bit_5 = CSRStorage()
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self.control_bit_6 = CSRStorage()
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self.control_bit_7 = CSRStorage()
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self.encoded_0 = CSRStatus(10)
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self.encoded_0 = CSRStatus(10)
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self.encoded_1 = CSRStatus(10)
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self.encoded_1 = CSRStatus(10)
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@ -97,19 +89,6 @@ class CXP(Module, AutoCSR):
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self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
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self.gtx.encoder.k[1].eq(self.control_bit_3.storage),
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counter.eq(0),
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counter.eq(0),
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),
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),
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# ).Elif(counter == 2,
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# self.gtx.encoder.d[0].eq(self.data_4.storage),
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# self.gtx.encoder.k[0].eq(self.control_bit_4.storage),
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# self.gtx.encoder.d[1].eq(self.data_5.storage),
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# self.gtx.encoder.k[1].eq(self.control_bit_5.storage),
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# counter.eq(counter+1),
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# ).Elif(counter == 3,
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# self.gtx.encoder.d[0].eq(self.data_6.storage),
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# self.gtx.encoder.k[0].eq(self.control_bit_6.storage),
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# self.gtx.encoder.d[1].eq(self.data_7.storage),
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# self.gtx.encoder.k[1].eq(self.control_bit_7.storage),
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# counter.eq(0),
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# ),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.encoded_0.status.eq(self.gtx.encoder.output[0]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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self.encoded_1.status.eq(self.gtx.encoder.output[1]),
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]
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]
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