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pipeline GW: increase buf len to 512 for event pak

This commit is contained in:
morgan 2024-10-07 17:18:43 +08:00
parent d46c5434de
commit 19fe570924
1 changed files with 4 additions and 6 deletions
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10
src/gateware/cxp_pipeline.py
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@ -11,7 +11,7 @@ word_dw = 32
word_layout = [("data", word_dw), ("k", word_dw//8)]
buffer_count = 4
buffer_depth = 128
buffer_depth = 512
def K(x, y):
return ((y << 5) | x)
@ -182,7 +182,7 @@ class Trigger_ACK_Inserter(Module):
@FullMemoryWE()
class TX_Command_Packet(Module, AutoCSR):
def __init__(self):
self.tx_word_len = CSRStorage(bits_for(buffer_depth))
self.tx_word_len = CSRStorage(log2_int(buffer_depth))
self.tx = CSR()
# # #
@ -193,7 +193,7 @@ class TX_Command_Packet(Module, AutoCSR):
tx_done = Signal()
addr_next = Signal(bits_for(buffer_depth))
addr_next = Signal(log2_int(buffer_depth))
addr = Signal.like(addr_next)
addr_rst = Signal()
addr_inc = Signal()
@ -419,14 +419,11 @@ class CXP_Data_Packet_Decode(Module):
self.write_ptr_sys = Signal.like(write_ptr)
self.specials += MultiReg(write_ptr, self.write_ptr_sys),
self.read_ptr_rx = Signal.like(write_ptr)
self.comb += [
mem_port.adr[:addr_nbits].eq(addr),
mem_port.adr[addr_nbits:].eq(write_ptr),
]
# For control ack, event packet
fsm.act("LOAD_BUFFER",
mem_port.we.eq(0),
@ -448,6 +445,7 @@ class CXP_Data_Packet_Decode(Module):
)
)
self.read_ptr_rx = Signal.like(write_ptr)
fsm.act("MOVE_BUFFER_PTR",
self.sink.ack.eq(0),
If(write_ptr + 1 == self.read_ptr_rx,