forked from M-Labs/artiq-zynq
zc706: si5324 is not needed for standalone target
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parent
e3d3cb2311
commit
18e05c91e1
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@ -11,7 +11,6 @@ from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import zc706
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from migen_axi.platforms import zc706
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from misoc.integration import cpu_interface
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from misoc.cores import gpio
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware import rtio, nist_clock, nist_qc2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
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@ -82,10 +81,6 @@ class ZC706(SoCCore):
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.rustc_cfg["HAS_SI5324"] = None
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.submodules.rtio_crg = RTIOCRG(self.platform, self.ps7.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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self.csr_devices.append("rtio_crg")
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self.rustc_cfg["has_rtio_crg_clock_sel"] = None
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self.rustc_cfg["has_rtio_crg_clock_sel"] = None
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