forked from M-Labs/artiq-zynq
sim: clean up
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parent
0c07a6525c
commit
18c16062b1
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@ -46,12 +46,12 @@ class Streams_Crossbar(Module):
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"WAIT_HEADER",
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"WAIT_HEADER",
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NextValue(self.stream_id, mux.source.dchar),
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NextValue(self.stream_id, mux.source.dchar),
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If(mux.source.stb,
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If(mux.source.stb,
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NextState("STREAM"),
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NextState("COPY"),
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),
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),
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)
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)
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fsm.act(
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fsm.act(
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"STREAM",
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"COPY",
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Case(self.stream_id, case),
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Case(self.stream_id, case),
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If(mux.source.eop,
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If(mux.source.eop,
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NextState("SWITCH_CONN"),
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NextState("SWITCH_CONN"),
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@ -223,9 +223,9 @@ class Stream_Parser(Module):
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fsm.act(
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fsm.act(
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"GET_PAK_TAG",
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"GET_PAK_TAG",
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self.sink.ack.eq(1),
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If(
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If(
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self.sink.stb,
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self.sink.stb,
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self.sink.ack.eq(1),
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NextValue(self.pak_tag, self.sink.dchar),
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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NextState("GET_PAK_SIZE_0"),
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),
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),
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