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upconn fw: add tx test packet csr control

This commit is contained in:
morgan 2024-09-11 10:17:26 +08:00
parent d9888d7647
commit 16ccd7eada
1 changed files with 11 additions and 9 deletions
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20
src/libboard_artiq/src/cxp_upconn.rs
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@ -19,7 +19,7 @@ impl From<IoError> for Error {
} }
pub fn tx_test(timer: &mut GlobalTimer) { pub fn tx_test(timer: &mut GlobalTimer) {
const LEN: usize = 4 * 20; const LEN: usize = 4 * 1000;
let mut pak_arr: [u8; LEN] = [0; LEN]; let mut pak_arr: [u8; LEN] = [0; LEN];
unsafe { unsafe {
@ -27,21 +27,23 @@ pub fn tx_test(timer: &mut GlobalTimer) {
// csr::cxp::upconn_bitrate2x_enable_write(1); // csr::cxp::upconn_bitrate2x_enable_write(1);
csr::cxp::upconn_clk_reset_write(0); csr::cxp::upconn_clk_reset_write(0);
send(&Packet::ControlU32Reg(Command::Read { addr: 0x00 })).expect("Cannot send CoaXpress packet"); // send(&Packet::ControlU32Reg(Command::Read { addr: 0x00 })).expect("Cannot send CoaXpress packet");
csr::cxp::upconn_tx_testmode_en_write(1);
csr::cxp::upconn_tx_enable_write(1); csr::cxp::upconn_tx_enable_write(1);
timer.delay_us(2); // send one word
csr::cxp::upconn_testseq_stb_write(1);
timer.delay_us(2); // timer.delay_us(2);
// DEBUG: Trigger packet // DEBUG: Trigger packet
let linktrig_mode: u8 = 0x01; // let linktrig_mode: u8 = 0x01;
csr::cxp::upconn_trig_delay_write(0x05); // csr::cxp::upconn_trig_delay_write(0x05);
csr::cxp::upconn_linktrigger_write(linktrig_mode); // csr::cxp::upconn_linktrigger_write(linktrig_mode);
csr::cxp::upconn_trig_stb_write(1); // send trig // csr::cxp::upconn_trig_stb_write(1); // send trig
// DEBUG: Trigger ACK packet // DEBUG: Trigger ACK packet
// csr::cxp::upconn_ack_write(1); // csr::cxp::upconn_ack_write(1);
timer.delay_us(20); timer.delay_us(2000);
csr::cxp::upconn_tx_enable_write(0); csr::cxp::upconn_tx_enable_write(0);
// Collect data // Collect data