forked from M-Labs/artiq-zynq
cxp upcxp: add tx_enable & startup sequence
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@ -6,17 +6,15 @@ from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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def K(x, y):
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return 1 << 8 | (y << 5) | x
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def D(x, y):
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return (y << 5) | x
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IDLE = [
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K(28, 5),
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K(28, 1),
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K(28, 1),
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D(21, 5),
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# CXP2.1 section 9.2.5
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IDLE_WORDS = [
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#[k, data]
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[0b10111100, 1], #K28.5
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[0b10111100, 1], #K28.5
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# TODO: fix index error for this crap
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[0b00111100, 1], #K28.1
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[0b00111100, 1], #K28.1
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# Cat(0b10111100, 0), #D28.5
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]
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@ -25,6 +23,7 @@ class CXP_UpConn(Module, AutoCSR):
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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self.tx_enable = CSRStorage()
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self.tx_fifos = []
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@ -91,87 +90,87 @@ class CXP_UpConn(Module, AutoCSR):
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(sources_stb)
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p = Signal(max=len(IDLE))
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# self.sync.cxp_upconn +=[
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# # TODO: use reduce(or, tx_fifos_stbs)
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# # self.phy.sink.stb.eq(self.tx_fifos[0].source.stb | self.tx_fifos[1].source.stb | self.tx_fifos[2].source.stb),
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# # TODO: add tx_enable like gtx?
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# # self.phy.sink.stb.eq(1),
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# self.phy.sink.stb.eq(0),
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# If(~self.phy.sink.ack, #PHY sink not full i.e. ready to receive data
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# If(~self.pe.n,
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# self.phy.sink.data.eq(tx_fifos_datas[self.pe.o]),
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# tx_fifos_ack[self.pe.o].eq(1),
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# self.phy.sink.stb.eq(1),
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# )
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# # ).Else(
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# # self.phy.sink.data.eq(Array(IDLE)[p]),
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# # If(p != len(IDLE),
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# # p.eq(p+1)
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# # ).Else(
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# # p.eq(0),
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# # )
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# # ),
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# ),
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# ]
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idle_word_count = Signal(max=len(IDLE_WORDS))
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self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules += fsm
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o = Signal()
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tx_busy = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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encoded = Signal()
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stb = Signal()
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fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable.storage,
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NextState("ENCODE_IDLE_WORD")
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)
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)
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fsm.act("ENCODE_IDLE_WORD",
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NextValue(self.encoder.d, IDLE_WORDS[0][0]),
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NextValue(self.encoder.k, IDLE_WORDS[0][1]),
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NextValue(self.encoder.disp_in, 0),
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NextValue(idle_word_count, 1),
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NextState("START_TX")
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)
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fsm.act("START_TX",
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tx_en.eq(1),
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If((~self.tx_enable.storage) & (tx_bitcount == 9),
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NextState("WAIT_TX_ENABLE")
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)
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)
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self.sync.cxp_upconn +=[
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encoded.eq(0),
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If(~tx_busy & ~encoded & ~self.pe.n,
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self.encoder.d.eq(sources_data[self.pe.o][:8]),
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self.encoder.k.eq(sources_data[self.pe.o][8]),
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sources_ack[self.pe.o].eq(1),
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encoded.eq(1),
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).Elif(~tx_busy & encoded,
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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tx_busy.eq(1),
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).Elif(tx_busy,
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If(tx_en,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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If((tx_bitcount == 8) & ~self.pe.n,
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If(tx_bitcount == 8,
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If(~self.pe.n,
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self.encoder.d.eq(sources_data[self.pe.o][:8]),
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self.encoder.k.eq(sources_data[self.pe.o][8]),
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sources_ack[self.pe.o].eq(1),
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encoded.eq(1),
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).Else(
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self.encoder.d.eq(Array(IDLE_WORDS)[idle_word_count][0]),
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self.encoder.k.eq(Array(IDLE_WORDS)[idle_word_count][1]),
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If(idle_word_count != len(IDLE_WORDS),
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idle_word_count.eq(idle_word_count + 1)
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).Else(
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idle_word_count.eq(0)
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)
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)
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).Elif(tx_bitcount == 9,
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If(encoded,
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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)
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).Else(
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tx_busy.eq(0),
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o.eq(0),
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)
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)
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o.eq(0)
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)
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]
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# DEBUG: remove pads
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self.idle_word_index = CSRStatus()
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self.sync.cxp_upconn +=[
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self.idle_word_index.status.eq(idle_word_count)
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]
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ninth_bit = Signal()
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eighth_bit = Signal()
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idle_3 = Signal()
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idle_2 = Signal()
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self.comb += [
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eighth_bit.eq(tx_bitcount == 8),
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ninth_bit.eq(tx_bitcount == 9),
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idle_3.eq(idle_word_count == 3),
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idle_2.eq(idle_word_count == 2),
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]
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self.specials += [
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# debug sma
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@ -181,9 +180,11 @@ class CXP_UpConn(Module, AutoCSR):
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# pmod 0-7 pin
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Instance("OBUF", i_I=o, o_O=pmod[0]),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
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Instance("OBUF", i_I=tx_busy, o_O=pmod[2]),
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Instance("OBUF", i_I=eighth_bit, o_O=pmod[3]),
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Instance("OBUF", i_I=ninth_bit, o_O=pmod[4]),
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Instance("OBUF", i_I=tx_en, o_O=pmod[2]),
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Instance("OBUF", i_I=idle_3, o_O=pmod[3]),
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Instance("OBUF", i_I=idle_2, o_O=pmod[4]),
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# Instance("OBUF", i_I=eighth_bit, o_O=pmod[3]),
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# Instance("OBUF", i_I=ninth_bit, o_O=pmod[4]),
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Instance("OBUF", i_I=encoded, o_O=pmod[5]),
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Instance("OBUF", i_I=~self.pe.n, o_O=pmod[6]),
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]
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@ -212,56 +213,8 @@ class UpConnTXPHY(Module, AutoCSR):
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]
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o = Signal()
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tx_busy = Signal()
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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self.specials += Instance("OBUF", i_I=o, o_O=pads.p_tx)
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self.sync.cxp_upconn +=[
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If(~tx_busy & ~self.sink.stb,
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self.sink.ack.eq(0),
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).Elif(~tx_busy & self.sink.stb,
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self.sink.ack.eq(1),
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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tx_busy.eq(1),
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).Elif(tx_busy,
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# outputing data
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 7,
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self.sink.ack.eq(0), # ready to receive data
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).Elif(tx_bitcount == 9,
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If(self.sink.stb,
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# got stb signal i.e. is full
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self.sink.ack.eq(1),
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tx_bitcount.eq(0),
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tx_reg.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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).Else(
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tx_busy.eq(0),
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o.eq(0),
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)
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)
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)
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# If(tx_bitcount != 9,
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# tx_bitcount.eq(tx_bitcount + 1),
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# ).Elif(self.sink.stb,
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# tx_busy.eq(1),
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# tx_bitcount.eq(0),
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# tx_reg.eq(self.encoder.output),
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# self.encoder.disp_in.eq(self.encoder.disp_out),
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# self.sink.ack.eq(1),
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# ).Else(
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# self.sink.ack.eq(1), # sink is empty
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# tx_busy.eq(0),
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# o.eq(0)
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# )
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]
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