forked from M-Labs/artiq-zynq
downconn GW: rename to PHY
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@ -10,7 +10,7 @@ from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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from functools import reduce
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from operator import add
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class CXP_DownConn(Module, AutoCSR):
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class CXP_DownConn_PHY(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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nconn = len(pads)
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self.rx_start_init = CSRStorage()
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