forked from M-Labs/artiq-zynq
cxp: add upconn pads
This commit is contained in:
parent
75407b2ff4
commit
1331281e5c
|
@ -6,15 +6,15 @@ from cxp_downconn import CXP_DownConn
|
|||
from cxp_upconn import CXP_UpConn
|
||||
|
||||
class CXP(Module, AutoCSR):
|
||||
def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
|
||||
def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
|
||||
self.submodules.crc = CXP_CRC(8)
|
||||
# FIFOs with transmission priority
|
||||
# 0: Trigger packet
|
||||
# 1: IO acknowledgment for trigger packet
|
||||
# 2: All other packets
|
||||
self.submodules.upconn = CXP_UpConn(debug_sma, sys_clk_freq, pmod_pads)
|
||||
self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
|
||||
self.submodules.downconn = CXP_DownConn(refclk, pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||
|
||||
|
||||
class CXP_CRC(Module, AutoCSR):
|
||||
|
|
Loading…
Reference in New Issue