forked from M-Labs/artiq-zynq
cxp: add upconn pads
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75407b2ff4
commit
1331281e5c
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@ -6,15 +6,15 @@ from cxp_downconn import CXP_DownConn
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from cxp_upconn import CXP_UpConn
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from cxp_upconn import CXP_UpConn
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class CXP(Module, AutoCSR):
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class CXP(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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self.submodules.crc = CXP_CRC(8)
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self.submodules.crc = CXP_CRC(8)
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# FIFOs with transmission priority
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# FIFOs with transmission priority
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# 0: Trigger packet
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# 0: Trigger packet
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# 1: IO acknowledgment for trigger packet
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# 1: IO acknowledgment for trigger packet
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# 2: All other packets
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# 2: All other packets
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self.submodules.upconn = CXP_UpConn(debug_sma, sys_clk_freq, pmod_pads)
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self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn(refclk, pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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class CXP_CRC(Module, AutoCSR):
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class CXP_CRC(Module, AutoCSR):
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