diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py index 192c5f6..aaeba50 100644 --- a/src/gateware/cxp_pipeline.py +++ b/src/gateware/cxp_pipeline.py @@ -305,8 +305,10 @@ class RX_Debug_Buffer(Module,AutoCSR): class CXP_Data_Packet_Decode(Module): def __init__(self): self.packet_type = Signal(8) + self.decode_err = Signal() self.test_err = Signal() + self.buffer_err = Signal() # # # # DEBUG: remove debug @@ -417,6 +419,8 @@ class CXP_Data_Packet_Decode(Module): self.write_ptr_sys = Signal.like(write_ptr) self.specials += MultiReg(write_ptr, self.write_ptr_sys), + self.read_ptr_rx = Signal.like(write_ptr) + self.comb += [ mem_port.adr[:addr_nbits].eq(addr), mem_port.adr[addr_nbits:].eq(write_ptr), @@ -429,16 +433,32 @@ class CXP_Data_Packet_Decode(Module): self.sink.ack.eq(1), If(self.sink.stb, If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)), - NextValue(write_ptr, write_ptr + 1), - NextState("IDLE"), + NextState("MOVE_BUFFER_PTR"), ).Else( mem_port.we.eq(1), mem_port.dat_w.eq(self.sink.data), NextValue(addr, addr + 1), + + If(addr == buffer_depth - 1, + # discard the packet + self.buffer_err.eq(1), + NextState("IDLE"), + ) ) ) ) + fsm.act("MOVE_BUFFER_PTR", + self.sink.ack.eq(0), + If(write_ptr + 1 == self.read_ptr_rx, + # if next one hasn't been read, overwrite the current buffer when new packet comes in + self.buffer_err.eq(1), + ).Else( + NextValue(write_ptr, write_ptr + 1), + ), + NextState("IDLE"), + ) + class CXP_Trig_Ack_Checker(Module, AutoCSR): def __init__(self): self.sink = stream.Endpoint(word_layout)