forked from M-Labs/artiq-zynq
cxp downconn: refactor bruteforce aligner
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dbce74d831
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@ -104,10 +104,10 @@ class CXP_DownConn(Module, AutoCSR):
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Instance("OBUF", i_I=gtx.clk_aligner.rxslide, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=gtx.clk_aligner.rxinit_done, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=gtx.clk_aligner.restart, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_det.comma_aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_aligned, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=gtx.clk_aligner.ready, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_det.reset, o_O=pmod_pads[5]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_det.detected, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=gtx.clk_aligner.comma_det_reset, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=gtx.clk_aligner.comma_det.detected, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=, o_O=pmod_pads[7]),
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]
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@ -162,9 +162,9 @@ class CXP_DownConn(Module, AutoCSR):
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self.rxdata_1.status.eq(self.gtx.decoders[1].input),
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self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
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self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
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If(self.gtx.clk_aligner.comma_det.detected,
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self.shifted.status.eq(self.gtx.clk_aligner.comma_det.bitshift),
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)
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# If(self.gtx.clk_aligner.comma_det.detected,
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# self.shifted.status.eq(self.gtx.clk_aligner.comma_det.bitshift),
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# )
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]
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@ -299,8 +299,16 @@ class Comma_Detector(Module):
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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# 50000 62.5MHz locks | 125MHz takes a lot time to locks | 250MHz many commas
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# 30000 62.5MHz & 125MHz locks | 250MHz more commas but not lock
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# 30000 62.5MHz & 125MHz locks | 250MHz nothing to see
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# 27000 62.5MHz & 125MHz locks | 250MHz nothing to see
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# 25000 62.5MHz takes long time to lock | 125MHz no lock | 250MHz locks
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# 24700 62.5MHz lock | 125MHz sometimes locks | 250MHz locks
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# 20000 250MHz nothing to see
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# 10000 62.5MHz & 125MHz nothing to see | 250MHz many commas not much can survive the second check
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class Manual_Aligner(Module):
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def __init__(self, comma, check_period=50_000, width=20):
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def __init__(self, comma, check_period=24_700, width=20):
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self.rxslide = Signal()
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self.data = Signal(width)
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self.rxinit_done = Signal()
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@ -310,24 +318,29 @@ class Manual_Aligner(Module):
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# # #
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self.submodules.restart_ps = restart_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
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timerout_period = 5_000_000
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timerout = Signal(reset=timerout_period-1, max=timerout_period)
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ready_sys = Signal()
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self.specials += MultiReg(self.ready, ready_sys)
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ready_rxclk = Signal()
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self.specials += MultiReg(ready_rxclk, self.ready)
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self.ready.attr.add("no_retiming")
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restart_sys = Signal()
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restart_rxclk = Signal()
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self.specials += MultiReg(restart_rxclk, restart_sys)
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restart_sys.attr.add("no_retiming")
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# NOTE: be careful of all the timeout values!!! It should be much larger than the longest fsm
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# TODO: fix comma fall too fast for 500MHz (10Gpbs) -> need to change CDR_CFG via DRP
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# Restart rx periodically since rx need to be restart when connecting RXN/RXP
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self.sync += [
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self.restart.eq(0),
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If(restart_ps.o,
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If(restart_sys,
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timerout.eq(timerout.reset),
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self.restart.eq(1),
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),
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If(~ready_sys,
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).Elif(~self.ready,
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If((timerout == 0),
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timerout.eq(timerout.reset),
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self.restart.eq(1),
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@ -337,115 +350,67 @@ class Manual_Aligner(Module):
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)
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]
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self.comma_det_reset = Signal()
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self.comma_aligned = Signal()
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self.submodules.comma_det = comma_det = ClockDomainsRenamer("cxp_gtx_rx")(Comma_Detector(comma, width))
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self.comb += comma_det.data.eq(self.data)
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comma_n = ~comma & 0b1111111111
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self.sync.cxp_gtx_rx += [
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If(self.comma_det_reset,
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self.comma_aligned.eq(0)
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).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
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self.comma_aligned.eq(1)
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),
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]
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# minimum of 32 RXUSRCLK2 cycles are required between two RXSLIDE pulses
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# There is latency between the slide and the slide result at RXDATA
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# Max = 967.5 UI
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# see 42662 - 7 Series GTX Transceivers - TX and RX Latency Values
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# https://support.xilinx.com/s/article/42662?language=en_US
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self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(64))
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# DS191 (v1.18.1) Table 95
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# Tlock = 50000 UI
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self.submodules.cdr_stable_timer = cdr_stable_timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(check_period))
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self.submodules.fsm = fsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="IDLE"))
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# NOTE: if this is connected to PMOD it will work on 250MHz
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# BUG: somehow the comma det doesn't work after the cdr_stable_timer :( thus, waiting for the timeout to happen
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# (which I know from bruteforcealigner, doesn't work well :( )
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rxinit_done_rxclk = Signal()
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self.specials += MultiReg(self.rxinit_done, rxinit_done_rxclk, odomain="cxp_gtx_rx")
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check_timer = Signal(reset=check_period-1,max=check_period)
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slide_counter = Signal(max=width)
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fsm.act("IDLE",
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comma_det.reset.eq(1),
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self.comma_det_reset.eq(1),
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If(rxinit_done_rxclk,
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NextValue(check_timer, check_timer.reset),
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NextState("WAIT_COMMA_DET"),
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),
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)
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fsm.act("WAIT_COMMA_DET",
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cdr_stable_timer.wait.eq(1),
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If(cdr_stable_timer.done,
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If(comma_det.comma_aligned,
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NextState("READY")
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).Else(
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restart_ps.i.eq(1),
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NextState("IDLE"),
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)
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),
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NextValue(check_timer, check_timer - 1),
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If(check_timer == 0,
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restart_rxclk.eq(1),
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NextState("RESET"),
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# restart_ps.i.eq(1),
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# NextState("IDLE"),
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).Elif(self.comma_aligned,
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NextValue(check_timer, check_timer.reset),
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self.comma_det_reset.eq(1),
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NextState("READY")
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)
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)
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fsm.act("READY",
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self.ready.eq(1),
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ready_rxclk.eq(1),
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If(check_timer == 0,
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NextValue(check_timer, check_timer.reset),
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comma_det.reset.eq(1),
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If(~comma_det.comma_aligned,
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restart_ps.i.eq(1),
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NextState("IDLE"),
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self.comma_det_reset.eq(1),
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If(~self.comma_aligned,
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restart_rxclk.eq(1),
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NextState("RESET"),
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# restart_ps.i.eq(1),
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# NextState("IDLE"),
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)
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).Else(
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NextValue(check_timer, check_timer - 1),
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)
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)
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# fsm.act("IDLE",
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# comma_det.reset.eq(1),
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# If(rxinit_done_rxclk,
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# cdr_stable_timer.wait.eq(1),
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# If(cdr_stable_timer.done,
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# NextState("WAIT_COMMA_DET"),
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# ),
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# ),
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# )
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# fsm.act("WAIT_COMMA_DET",
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# If(comma_det.detected,
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# NextValue(slide_counter, comma_det.bitshift),
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# NextState("SLIDING")
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# )
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# )
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# fsm.act("SLIDING",
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# comma_det.reset.eq(1),
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# If(slide_counter == 0,
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# NextValue(check_timer, check_timer.reset),
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# NextState("READY")
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# ).Else(
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# NextValue(slide_counter, slide_counter - 1),
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# self.rxslide.eq(1),
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# NextState("WAIT_DATA_SLIDE"),
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# )
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# )
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# fsm.act("WAIT_DATA_SLIDE",
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# comma_det.reset.eq(1),
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# timer.wait.eq(1),
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# If(timer.done,
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# NextState("SLIDING"),
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# )
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# )
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# fsm.act("READY",
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# self.ready.eq(1),
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# If(check_timer == 0,
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# NextValue(check_timer, check_timer.reset),
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# comma_det.reset.eq(1),
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# If(~comma_det.comma_aligned,
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# restart_ps.i.eq(1),
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# NextState("IDLE"),
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# )
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# ).Else(
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# NextValue(check_timer, check_timer - 1),
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# )
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# )
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fsm.act("RESET",
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restart_rxclk.eq(1),
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)
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class GTX(Module):
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@ -593,7 +558,7 @@ class GTX(Module):
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled
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i_RXLPMEN=1, # RXLPMEN = 1: LPM mode is enabled for non scramble data
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p_RX_DFE_GAIN_CFG=0x0207EA,
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p_RX_DFE_VP_CFG=0b00011111100000011,
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p_RX_DFE_UT_CFG=0b10001000000000000,
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