diff --git a/src/libboard_artiq/src/si549.rs b/src/libboard_artiq/src/si549.rs
index cb77118..1227ff9 100644
--- a/src/libboard_artiq/src/si549.rs
+++ b/src/libboard_artiq/src/si549.rs
@@ -552,7 +552,6 @@ pub mod wrpll {
 pub mod sma_pll {
     use super::*;
 
-    // Based on "DRP State Machine" section from XAPP888
     mod mmcm {
 
         use super::*;
@@ -572,6 +571,12 @@ pub mod sma_pll {
             }
         }
 
+        fn set_data(value: u16) {
+            unsafe {
+                csr::sma_pll::drp_in_write(value);
+            }
+        }
+
         fn set_enable(en: bool) {
             unsafe {
                 let val = if en { 1 } else { 0 };
@@ -579,6 +584,13 @@ pub mod sma_pll {
             }
         }
 
+        fn set_write_enable(en: bool) {
+            unsafe {
+                let val = if en { 1 } else { 0 };
+                csr::sma_pll::drp_w_en_write(val);
+            }
+        }
+
         fn get_data() -> u16 {
             unsafe { csr::sma_pll::drp_out_read() }
         }
@@ -588,10 +600,12 @@ pub mod sma_pll {
         }
 
         pub fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
+            // Based on "DRP State Machine" from XAPP888
             set_addr(address);
             set_enable(true);
             // Set DADDR on the MMCM and assert DEN for one clock cycle
             one_clock_cycle(timer);
+
             set_enable(false);
             while !drp_ready() {
                 // keep the clock signal until data is ready
@@ -599,6 +613,23 @@ pub mod sma_pll {
             }
             get_data()
         }
+
+        pub fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
+            // Based on "DRP State Machine" from XAPP888
+            set_addr(address);
+            set_data(value);
+            set_write_enable(true);
+            set_enable(true);
+            // Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle
+            one_clock_cycle(timer);
+
+            set_write_enable(false);
+            set_enable(false);
+            while !drp_ready() {
+                // keep the clock signal until write is finished
+                one_clock_cycle(timer);
+            }
+        }
     }
 
     pub fn setup(timer: &mut GlobalTimer) {