diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 14e0a1f..a529f4b 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -165,11 +165,6 @@ class DownConn_Interface(Module, AutoCSR):
         ]
 
 
-        # DEBUG: tx loopback fifo control
-        self.tx_stb = CSRStorage()
-        self.sync += phy.tx_stb_sys.eq(self.tx_stb.storage) 
-   
-
         # DEBUG: Transmission Pipeline
         # 
         #  rtio pak  ----+
@@ -183,20 +178,14 @@ class DownConn_Interface(Module, AutoCSR):
 
         # DEBUG: TX pipeline
         self.submodules.bootstrap_loopback = bootstrap_loopback = TX_Bootstrap()
-        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
         self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
         self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
 
         self.ack = CSR()
-        self.mux_sel = CSRStorage()
 
         self.sync += trig_ack.stb.eq(self.ack.re),
-        self.comb += [
-            bootstrap_loopback.source.connect(mux.sink0),
-            mux.sel.eq(self.mux_sel.storage),
-        ]
 
-        tx_pipeline = [mux , pak_wrp, trig_ack, phy]
+        tx_pipeline = [bootstrap_loopback, pak_wrp, trig_ack, phy]
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
@@ -205,17 +194,20 @@ class DownConn_Interface(Module, AutoCSR):
 
         # Receiver Pipeline WIP
         # 
-        #        32                32
-        # PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet  ------> debug buffer
-        #                                checker             decoder
+        #        32             32+8(dchar)
+        # PHY ---/---> dchar   -----/-----> trigger ack ------>  packet  ------> CDC FIFO ------> debug buffer
+        #              decoder              checker              decoder
         #
         cdr = ClockDomainsRenamer("cxp_gtx_rx")
 
+        # decode all incoming data as duplicate char and inject the result into the bus for downstream modules
+        self.submodules.dchar_decoder = dchar_decoder = cdr(Duplicated_Char_Decoder())
+
         # Priority level 1 packet - Trigger ack packet
-        self.submodules.trig_ack_checker = trig_ack_checker = cdr(CXP_Trig_Ack_Checker())
+        self.submodules.trig_ack_checker = trig_ack_checker = cdr(Trigger_Ack_Checker())
         
         self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
-        self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
+        self.sync.cxp_gtx_rx += trig_ack_ps.i.eq(trig_ack_checker.ack)
 
         self.trig_ack = Signal()
         self.trig_clr = Signal()
@@ -239,7 +231,7 @@ class DownConn_Interface(Module, AutoCSR):
         test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
         self.submodules += decode_err_ps, test_err_ps, buffer_err_ps
-        self.comb += [
+        self.sync.cxp_gtx_rx += [
             decode_err_ps.i.eq(bootstrap.decode_err),
             test_err_ps.i.eq(bootstrap.test_err),
             buffer_err_ps.i.eq(bootstrap.buffer_err),
@@ -282,23 +274,11 @@ class DownConn_Interface(Module, AutoCSR):
         ]
         
 
-        # DEBUG: remove this cdc fifo
-        cdc_fifo = stream.AsyncFIFO(word_layout, 512)
+        cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
         self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
         self.submodules.debug_out = debug_out = RX_Debug_Buffer()
 
-        self.dmux_sel = CSRStorage()
-        self.submodules.dmux = dmux = stream.Demultiplexer(word_layout, 2)
-
-
-        self.comb += [
-            dmux.source0.connect(bootstrap.sink),
-            dmux.source1.connect(cdc_fifo.sink),
-            cdc_fifo.source.connect(debug_out.sink),
-            dmux.sel.eq(self.dmux_sel.storage),
-        ]
-
-        rx_pipeline = [phy, trig_ack_checker, dmux]
+        rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap, cdc_fifo, debug_out]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
         
@@ -319,8 +299,8 @@ class DownConn_Interface(Module, AutoCSR):
             # Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
             # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
             # # pmod 0-7 pin
-            Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
-            Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
+            # Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
             # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
             # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
             # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),