forked from M-Labs/artiq-zynq
cxp GW: rename to downconn phy
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@ -2,7 +2,7 @@ from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from cxp_downconn import CXP_DownConn
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from cxp_downconn import CXP_DownConn_PHY
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from cxp_upconn import CXP_UpConn_PHY
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from cxp_pipeline import *
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@ -10,7 +10,7 @@ class CXP(Module, AutoCSR):
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def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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self.submodules.upconn = UpConn_Interface(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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# TODO: support the option high speed upconn
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# TODO: add link layer
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