forked from M-Labs/artiq-zynq
wrpll gw: remove debug leftover
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@ -99,7 +99,6 @@ class SkewTester(Module, AutoCSR):
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class WRPLL(Module, AutoCSR):
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def __init__(self, platform, cd_ref, main_clk_se, COUNTER_BIT=32):
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self.refclk_reset = CSRStatus()
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self.helper_reset = CSRStorage(reset=1)
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self.ref_tag = CSRStatus(COUNTER_BIT)
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self.main_tag = CSRStatus(COUNTER_BIT)
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@ -113,8 +112,6 @@ class WRPLL(Module, AutoCSR):
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# # #
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self.sync += self.refclk_reset.status.eq(cd_ref.rst)
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self.submodules.main_dcxo = Si549(platform.request("ddmtd_main_dcxo_i2c"))
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self.submodules.helper_dcxo = Si549(platform.request("ddmtd_helper_dcxo_i2c"))
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