From 05761c53071859afbd5f5780fa7f052d289cd05a Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 3 Oct 2024 12:00:16 +0800
Subject: [PATCH] pipeline GW: expose writer_ptr

---
 src/gateware/cxp_pipeline.py | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index c0665d9..80fb0df 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -301,8 +301,10 @@ class RX_Debug_Buffer(Module,AutoCSR):
 class CXP_Data_Packet_Decode(Module):
     def __init__(self):
         self.packet_type = Signal(8)
-        self.decode_err = Signal()
+        self.write_ptr = Signal(bits_for(buffer_depth))
 
+        self.new_packet = Signal()
+        self.decode_err = Signal()
         self.test_err = Signal()
         # # #
 
@@ -338,6 +340,7 @@ class CXP_Data_Packet_Decode(Module):
         fsm.act("DECODE",
             self.sink.ack.eq(1),
             If(self.sink.stb,
+                self.new_packet.eq(1),
                 NextValue(self.packet_type, self.sink.data[:8]),
 
                 Case(self.sink.data[:8],{
@@ -393,20 +396,11 @@ class CXP_Data_Packet_Decode(Module):
             )      
         )
 
-        # TODO: add overflow error
-        # TODO: reclock this to cxp_gtx_rx
+        # A circular buffer for firmware to read packet from
         self.specials.mem = mem = Memory(word_dw, buffer_depth)
-        self.specials.mem_port = mem_port = mem.get_port(write_capable=True, clock_domain="sys")
+        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
 
-        # write pointer represents where the gateware is
-        write_ptr_rx = Signal(bits_for(buffer_depth))
-        # read pointer represents where CPU is
-        # write reaching read is an error, read reaching write is buffer clear
-        self.read_ptr_rx = Signal.like(write_ptr_rx)
-        self.new_packet_rx = Signal()
-
-        self.comb += mem_port.adr.eq(write_ptr_rx),
-        self.sync += self.new_packet_rx.eq(self.read_ptr_rx != write_ptr_rx)
+        self.comb += mem_port.adr.eq(self.write_ptr),
 
         # For control ack, event packet
         fsm.act("LOAD_BUFFER",
@@ -418,7 +412,7 @@ class CXP_Data_Packet_Decode(Module):
                 ).Else(
                     mem_port.we.eq(1),
                     mem_port.dat_w.eq(self.sink.data),
-                    NextValue(write_ptr_rx, write_ptr_rx + 1),
+                    NextValue(self.write_ptr, self.write_ptr + 1),
                 )
             )
         )