forked from M-Labs/artiq-zynq
cxp GW: use 16bits res width
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@ -320,7 +320,7 @@ class TX_Pipeline(Module, AutoCSR):
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class CXP_Frame_Pipeline(Module, AutoCSR):
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# optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
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# largest x/y pixel size supported by frame header are 24 bits
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def __init__(self, rx_pipelines, pmod_pads, roi_engine_count=1, res_width=24, count_width=31, packet_size=16384):
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def __init__(self, rx_pipelines, pmod_pads, roi_engine_count=1, res_width=16, count_width=31, packet_size=16384):
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n_downconn = len(rx_pipelines)
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assert n_downconn > 0
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assert count_width <= 31
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