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downconn GW: rename to RXPHYs

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morgan 2025-01-14 13:04:04 +08:00
parent 17de7f2365
commit 034588ec59
1 changed files with 5 additions and 5 deletions
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10
src/gateware/cxp_downconn.py
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@ -12,14 +12,14 @@ from cxp_pipeline import word_layout
from functools import reduce
from operator import add
class CXP_DownConn_PHYS(Module, AutoCSR):
class CXP_RXPHYs(Module, AutoCSR):
def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads, master=0):
self.qpll_reset = CSR()
self.qpll_locked = CSRStatus()
self.gtx_start_init = CSRStorage()
self.gtx_restart = CSR()
self.rx_phys = []
self.phys = []
# # #
# For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
@ -37,10 +37,10 @@ class CXP_DownConn_PHYS(Module, AutoCSR):
else:
rx_mode = "master" if i == master else "slave"
rx = Receiver(qpll, pad, sys_clk_freq, "single", rx_mode, debug_sma, pmod_pads)
self.rx_phys.append(rx)
self.phys.append(rx)
setattr(self.submodules, "rx"+str(i), rx)
for i, phy in enumerate(self.rx_phys):
for i, phy in enumerate(self.phys):
if i == master:
self.comb += rx_resetter.rx_ready.eq(phy.gtx.rx_ready)
self.comb += [
@ -49,7 +49,7 @@ class CXP_DownConn_PHYS(Module, AutoCSR):
]
# master rx_init will lock up when slaves_phaligndone signal is not connected
self.submodules.rx_phase_alignment = GTXInitPhaseAlignment([rx_phy.gtx.rx_init for rx_phy in self.rx_phys])
self.submodules.rx_phase_alignment = GTXInitPhaseAlignment([rx_phy.gtx.rx_init for rx_phy in self.phys])
class Receiver(Module):
def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):