From 00e5d32d45633475c6339eae3ca7e1db0524d7b3 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 20 Jun 2024 14:56:28 +0800 Subject: [PATCH] cxp upconn: add priority lv1 fifo & refactor --- src/gateware/cxp_upconn.py | 114 +++++++++++++++++++++++-------------- 1 file changed, 72 insertions(+), 42 deletions(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index 3f011a5..f36fff9 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -7,7 +7,7 @@ from misoc.interconnect.csr import * from misoc.interconnect import stream class CXP_UpConn(Module, AutoCSR): - def __init__(self, pads, tx_width=10, tx_fifo_depth=16): + def __init__(self, pads, tx_fifo_depth=32): self.clock_domains.cd_cxp_upconn = ClockDomain() self.clk_reset = CSRStorage(reset=1) @@ -48,15 +48,15 @@ class CXP_UpConn(Module, AutoCSR): AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage) ] - self.symbol = CSR(9) - self.encoded = CSRStatus(tx_width) - self.tx_reg = CSRStatus(tx_width) + self.symbol0 = CSR(9) + self.symbol1 = CSR(9) - self.data = Signal(8) - self.k_symbol = Signal() - self.stb = Signal() + nfifos = 2 + + self.data = [ Signal(8) for _ in range(nfifos)] + self.k_symbol = [ Signal() for _ in range(nfifos)] + self.stb = [ Signal() for _ in range(nfifos)] - nfifos = 1 self.fifo_full = CSRStatus(nfifos) @@ -67,66 +67,96 @@ class CXP_UpConn(Module, AutoCSR): cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"}) # Priority Queue + # 0: Trigger packet + # 1: IO acknowledgment for trigger packet + # 2: All other packets for i in range(nfifos): fifo = cdr(stream.AsyncFIFO([("data", 9)], tx_fifo_depth)) + # fifo = stream.SyncFIFO([("data", 9)], tx_fifo_depth) self.tx_fifos.append(fifo) setattr(self.submodules, "tx_fifo" + str(i), fifo) self.sync += [ - fifo.sink.stb.eq(self.stb), - fifo.sink.data.eq(Cat(self.data, self.k_symbol)), + fifo.sink.stb.eq(self.stb[i]), + fifo.sink.data.eq(Cat(self.data[i], self.k_symbol[i])), self.fifo_full.status[i].eq(~fifo.sink.ack), - self.stb.eq(self.symbol.re), - self.data.eq(self.symbol.r[:8]), - self.k_symbol.eq(self.symbol.r[8]) ] + self.sync += [ + self.stb[0].eq(self.symbol0.re), + self.data[0].eq(self.symbol0.r[:8]), + self.k_symbol[0].eq(self.symbol0.r[8]), + self.stb[1].eq(self.symbol1.re), + self.data[1].eq(self.symbol1.r[:8]), + self.k_symbol[1].eq(self.symbol1.r[8]), + ] self.tx_fifo0_source_data = CSRStatus(9) + self.tx_fifo1_source_data = CSRStatus(9) + self.tx_fifo0_stb = CSRStatus() + self.tx_fifo1_stb = CSRStatus() - self.submodules.encoder = SingleEncoder(True) - - tx_busy = Signal() - data_ack = Signal() - data_stb = Signal() - + self.submodules.tx = UpConn_TX(pads) + self.comb += [ - data_stb.eq(self.tx_fifos[0].source.stb), - If(self.tx_fifos[0].source.stb, - self.encoder.d.eq(self.tx_fifos[0].source.data[:8]), - self.encoder.k.eq(self.tx_fifos[0].source.data[8]), - self.tx_fifos[0].source.ack.eq(data_ack), - ), - # TODO: add idle & other fifo here - self.tx_fifo0_source_data.status.eq(self.tx_fifos[0].source.data) + self.tx_fifo0_source_data.status.eq(self.tx_fifos[0].source.data), + self.tx_fifo1_source_data.status.eq(self.tx_fifos[1].source.data), + self.tx_fifo0_stb.status.eq(self.tx_fifos[0].source.stb), + self.tx_fifo1_stb.status.eq(self.tx_fifos[1].source.stb), ] - o = Signal() - tx_bitcount = Signal(max=tx_width) - tx_reg = Signal(tx_width) - self.sync.cxp_upconn +=[ - self.encoded.status.eq(self.encoder.output), - data_ack.eq(0), + self.tx.data_stb.eq(self.tx_fifos[0].source.stb | self.tx_fifos[1].source.stb), + self.tx_fifos[0].source.ack.eq(0), + self.tx_fifos[1].source.ack.eq(0), + If(self.tx.data_ack, + If(self.tx_fifos[0].source.stb, + self.tx.encoder.d.eq(self.tx_fifos[0].source.data[:8]), + self.tx.encoder.k.eq(self.tx_fifos[0].source.data[8]), + self.tx_fifos[0].source.ack.eq(1), + ).Elif(self.tx_fifos[1].source.stb, + self.tx.encoder.d.eq(self.tx_fifos[1].source.data[:8]), + self.tx.encoder.k.eq(self.tx_fifos[1].source.data[8]), + self.tx_fifos[1].source.ack.eq(1), + ), + ), + ] + + # DEBUG: remove pads + self.specials += Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx) + +class UpConn_TX(Module, AutoCSR): + def __init__(self, pads): + self.data_ack = Signal() + self.data_stb = Signal() + self.data_out = CSRStatus(10) + + # # # + + self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True)) + + o = Signal() + tx_busy = Signal() + tx_bitcount = Signal(max=10) + tx_reg = Signal(10) + + self.sync.cxp_upconn +=[ + self.data_ack.eq(0), If(tx_busy, o.eq(tx_reg[0]), tx_reg.eq(Cat(tx_reg[1:], 0)) ), - If(tx_bitcount != tx_width - 1, + If(tx_bitcount != 9, tx_bitcount.eq(tx_bitcount + 1), - ).Elif(data_stb, + ).Elif(self.data_stb, tx_busy.eq(1), tx_bitcount.eq(0), tx_reg.eq(self.encoder.output), - self.tx_reg.status.eq(self.encoder.output), + self.data_out.status.eq(self.encoder.output), self.encoder.disp_in.eq(self.encoder.disp_out), - data_ack.eq(1), + self.data_ack.eq(1), ).Else( tx_busy.eq(0), o.eq(0) ) ] - # DEBUG: remove pads - self.specials += [ - Instance("OBUF", i_I=o, o_O=pads.p_tx), - Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx) - ] + self.specials += Instance("OBUF", i_I=o, o_O=pads.p_tx)