2021-02-07 14:44:09 +08:00
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#!/usr/bin/env python
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import argparse
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from operator import itemgetter
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from migen import *
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from migen.build.generic_platform import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from migen_axi.integration.soc_core import SoCCore
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from migen_axi.platforms import kasli_soc
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from misoc.interconnect.csr import *
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from misoc.integration import cpu_interface
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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import dma
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import analyzer
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import acpki
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class RTIOCRG(Module, AutoCSR):
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def __init__(self, platform):
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self.pll_reset = CSRStorage(reset=1)
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self.pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += [
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Instance("IBUFGDS",
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p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
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i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se),
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]
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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fb_clk = Signal()
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_BANDWIDTH="HIGH",
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p_REF_JITTER1=0.001,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN2=clk_synth_se,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=0,
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# VCO @ 1.5GHz when using 125MHz input
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p_CLKFBOUT_MULT=12, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=fb_clk,
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i_RST=self.pll_reset.storage,
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o_CLKFBOUT=fb_clk,
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p_CLKOUT0_DIVIDE=3, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=12, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=rtio_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self.pll_locked.status)
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]
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2021-02-07 22:34:29 +08:00
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eem_iostandard_dict = {
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0: "LVDS_25",
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1: "LVDS_25",
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2: "LVDS",
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3: "LVDS",
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4: "LVDS",
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5: "LVDS",
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6: "LVDS",
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7: "LVDS",
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8: "LVDS_25",
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9: "LVDS_25",
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10: "LVDS",
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11: "LVDS",
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}
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def eem_iostandard(eem):
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return IOStandard(eem_iostandard_dict[eem])
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2021-02-07 14:44:09 +08:00
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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ident = self.__class__.__name__
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if self.acpki:
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
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platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
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platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.submodules.rtio_crg = RTIOCRG(self.platform)
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self.csr_devices.append("rtio_crg")
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self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
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self.platform.add_false_path_constraints(
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self.ps7.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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2021-02-07 22:34:29 +08:00
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eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
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2021-02-15 19:56:59 +08:00
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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2021-02-07 14:44:09 +08:00
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self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
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self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
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self.csr_devices.append("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.csr_devices.append("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
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self.csr_devices.append("rtio_moninj")
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self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
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self.ps7.s_axi_hp1)
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericMaster(SoCCore):
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def __init__(self, description, **kwargs):
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raise NotImplementedError
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class GenericSatellite(SoCCore):
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def __init__(self, description, **kwargs):
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raise NotImplementedError
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def write_csr_file(soc, filename):
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with open(filename, "w") as f:
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f.write(cpu_interface.get_csr_rust(
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soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for generic Kasli-SoC systems")
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parser.add_argument("-r", default=None,
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help="build Rust interface into the specified file")
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parser.add_argument("-c", default=None,
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help="build Rust compiler configuration into the specified file")
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parser.add_argument("-g", default=None,
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help="build gateware into the specified directory")
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parser.add_argument("--acpki", default=False, action="store_true",
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help="enable ACPKI")
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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args = parser.parse_args()
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description = jsondesc.load(args.description)
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if description["target"] != "kasli_soc":
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raise ValueError("Description is for a different target")
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if description["base"] == "standalone":
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cls = GenericStandalone
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elif description["base"] == "master":
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cls = GenericMaster
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elif description["base"] == "satellite":
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cls = GenericSatellite
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else:
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raise ValueError("Invalid base")
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soc = cls(description, acpki=args.acpki)
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soc.finalize()
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if args.r is not None:
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write_csr_file(soc, args.r)
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if args.c is not None:
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write_rustc_cfg_file(soc, args.c)
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if args.g is not None:
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soc.build(build_dir=args.g)
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if __name__ == "__main__":
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main()
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