artiq-zynq/cxp_note.md

# CXP

## Finished
- Upconn - Low speed serial 
  [x] Low speed serial PHY
    [x] 20.833Mbps & 41.666Mbps change
    [x] 8b10b encoder
  [x] TX Pipeline with priority transmission
    [x] Trigger
    [x] Trigger ack
    [x] Test & Ctrl packet with DMA
  [x] CTRL Packet serialize firmware
    [x] follow DRTIO DMA
    [x] check crc
- Downconn - GTX
  [x] GTX serial PHY
    [x] QPLL & GTX DRP to config linerate
    [x] Comma checker & restart rx
  [x] RX Pipeline with priority decoder
    [x] Trigger ack 
    [x] CTRL packet DMA with extra buffer
    [x] Connection test sequence checker
  [x] CTRL Packet deserialize firmware
    [x] follow DRTIO DMA
    [x] check crc
  [x] GTX Multilane setup
    [x] add tx/rx mode for gtx 
- Camera boostrap
  [x] get the CXP version
  [x] test connection
  [x] discovery other extension (links)
  [x] set bitrate
- Camera frame pipeline
  [x] CXP frame packet routing (maybe no need to routing non zero streaming id (we have ROI buildin anyways)?)
  [x] CXP CRC32 detection
  [x] Region of interest engine (32 bits mode)
      [x] pixel gearbox
      [x] pixel parser (xy pos)
      [x] Test out CXP trigger
        [x] 8, 10, 12 bits in white test image mode


## TODO
[] remove ALL debug tools
  [] flake.nix mod
  [] local_run.sh mod
### Gateware
[x] refactor error_cnt 
[x] Heartbeat (is it useful?? lol)
[x] rename circular buffer to slots
[x] use `from misoc.interconnect.stream import Endpoint` instead
[x] add __init__.py for cxp??
[] Try to fix tight s/h time pins
[] remove self.source.ack in fsm
  - seems to kill timing :V
[] multilane ROI
  [] Region of interest engine (n*32 bits mode)
  [] bus widener + fifo
[] remove pmod/debug_sma in fns args
[] rtio to getting the frame
  - O: trigger
  - I: frame

### Firmware (design with driver)
[x] API programming
[x] add tag handling for api calls
  - support lane reset in kernel using syscall
[] double check cfg gating
  [] add libboard_artiq/src/lib.rs cfg gating
[] Camera auto linkup/linkdown using threads
  [] Camera linkdown detection
  [] add mutex support for tx/rx camera programming (or block them when camera is not ready)
  [] add xml url printout in uart (so user can just download the xml using api)
  [] add heartbeat checking
[] add flashing LED (non-essential)
[] add PoCXP (non-essential)

### Coredevice Driver
[x] use camera test pattern black/white to verify roi https://docs.baslerweb.com/test-patterns
[x] test out 8/10/12 bit mode
[] support simple camera programming interface (Not real time)
  - basic i2c-like interface with read/write u32
[] add grabber like fns & docs


### PR
1. push the gtx init fix
2. push the cxp core to misoc
3. push the cxp rtio core to artiq-zynq & artiq