artiq-zynq/sim_test.py

from migen import *
from misoc.interconnect.csr import *
from misoc.interconnect import stream

class test(Module):
    def __init__(self):

        self.test_cnt = Signal(32, reset=0x03020100)

        self.sync += [
            self.test_cnt[:8].eq(self.test_cnt[:8] + 4),
            self.test_cnt[8:16].eq(self.test_cnt[8:16] + 4),
            self.test_cnt[16:24].eq(self.test_cnt[16:24] + 4),
            self.test_cnt[24:].eq(self.test_cnt[24:] + 4),
        ]



dut = test()


def packet_sim(packets=[]):

    for _ in range(0x100):
        yield
    
    assert True


def testbench():
    yield from packet_sim()


run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")