forked from M-Labs/artiq-zynq
92 lines
3.2 KiB
Python
92 lines
3.2 KiB
Python
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from sim_generator import CXPCRC32Inserter
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from src.gateware.cxp_frame_pipeline import *
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from src.gateware.cxp_pipeline import *
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class double_buffer_pipeline(Module):
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def __init__(self):
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fifo = stream.SyncFIFO(word_layout, 32)
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dchar_decoder = Duplicated_Char_Decoder()
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broadcaster = Stream_Broadcaster(1)
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pipeline = [fifo, dchar_decoder, broadcaster]
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self.submodules += pipeline
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.submodules.buffer = buffer = Buffer(word_layout_dchar)
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self.comb += broadcaster.sources[0].connect(buffer.sink)
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self.source = buffer.source
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# for sim, no backpressure
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self.comb += self.source.ack.eq(1)
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dut = double_buffer_pipeline()
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def packet_sim(packets=[]):
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print("=================TEST========================")
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sink = dut.sink
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cyc = len(packets)
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pak = packets
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for c in range(cyc):
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yield sink.data.eq(pak[c]["data"])
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yield sink.k.eq(pak[c]["k"])
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yield sink.stb.eq(1)
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if "eop" in pak[c]:
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yield sink.eop.eq(1)
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else:
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yield sink.eop.eq(0)
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yield
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# extra clk cycles
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for _ in range(cyc, cyc + 20):
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yield sink.data.eq(0)
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yield sink.k.eq(0)
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yield sink.stb.eq(0)
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yield sink.eop.eq(0)
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yield
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assert True
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def testbench():
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paks = [
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{"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(4, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(4, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
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{"data": C(0x7C7C7C7C, word_dw), "k": Replicate(1, 4)},
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{"data": C(0x01010101, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0xF6ACEF6A, word_dw), "k": Replicate(0, 4)},
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{"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(1, char_width), 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(8, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
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{"data": Replicate(C(8, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
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{"data": C(0x19191919, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x09090909, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x90909090, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x985EFDB2, word_dw), "k": Replicate(0, 4)},
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]
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yield from packet_sim(paks)
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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