artiq-zynq/sim_crc.py

from migen import *
from misoc.interconnect import stream
from sim_pipeline import *
from src.gateware.cxp_pipeline import *

dut = StreamData_Generator()


def check_case(packet=[], ack=0):
    print("=================TEST========================")
    for i, p in enumerate(packet):
        yield dut.sink.data.eq(p["data"])
        yield dut.sink.k.eq(p["k"])
        yield dut.sink.stb.eq(1)
        if "eop" in p:
            yield dut.sink.eop.eq(1)

        # CLK 
        yield

        sink = dut.sink
        source = dut.source
        crc = dut.crc_inserter.crc
        print(
            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
        )
    # extra clk cycles
    cyc = i + 1
    for i in range(cyc, cyc + 11):
        # yield has memory for some reason
        yield dut.sink.stb.eq(0)
        yield dut.source.ack.eq(1)
        yield
        print(
            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
        )
    assert True


def testbench():
    packet = [
        {"data": 0x0000_0004, "k": Replicate(0, 4)},
        {"data": 0x0000_0000, "k": Replicate(0, 4), "eop":1},
    ]
    yield from check_case(packet)


run_simulation(dut, testbench())