forked from M-Labs/artiq-zynq
29 lines
497 B
Python
29 lines
497 B
Python
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from migen import *
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from misoc.interconnect import stream
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class Frame(Module):
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def __init__(self):
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self.a = Signal()
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self.b = Signal()
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self.comb += [
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self.a.eq(self.b),
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# self.b.eq(self.a),
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]
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dut = Frame()
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def check_case():
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yield dut.a.eq(1)
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yield
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yield dut.a.eq(0)
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yield
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for i in range(10):
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yield
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def testbench():
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yield from check_case()
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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