mikelam pushed to master at sinara-hw/Syrostan-Lever-Ordering-Guide
- dac8eb0640 add background information; optimize layout format
mikelam
renamed repository from Syrostan-Leveler-Ordering-Guide
to sinara-hw/Syrostan-Lever-Ordering-Guide
mikelam pushed to master at sinara-hw/Syrostan-Lever-Ordering-Guide
- 2cfab3c915 init commit based on the Google Docs document writen by Jack Zheng
mikelam created repository sinara-hw/Syrostan-Lever-Ordering-Guide
mikelam pushed to master at sinara-hw/Syrostan
- 7a0fa5ce04 add TPS2590 to make 3v3_MP output controllable and limit current; update 12v output current limit to 1A
mikelam pushed to master at sinara-hw/Syrostan
- b3427d68c6 use 2x17 connector for FPGA_IO and 2x12 connector for Analog; use FPGA GBIN pins for FSMC and HSADC clocks
mikelam pushed to master at sinara-hw/Syrostan-MCU-C
- 34042d1c59 add eem0 and eem2 port support; eem0 input working
- cf76348432 EEM output working
- d64ae0e652 add time stamp (in ns) for plotting; ADC working at 80MHz
- a082a2bd0d use UART to transmit data out and plot wave using python for HSADC performance testing (working well @75MHz)
- 5d1c7c4d51 FPGA BRAM working
- Compare 11 commits »
mikelam pushed to master at sinara-hw/Syrostan-MCU-C
- 7b51c26a0e add eem0 and eem2 port support; eem0 input working
- 46d4c4358a EEM output working
- f635dd3e90 add time stamp (in ns) for plotting; ADC working at 80MHz
- ba31098bfd use UART to transmit data out and plot wave using python for HSADC performance testing (working well @75MHz)
- 6477f0d93b FPGA BRAM working
- Compare 10 commits »
mikelam created repository sinara-hw/Syrostan-MCU-C