forked from M-Labs/nac3
nac3artiq: support compiling for the host
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parent
558c3f03ef
commit
8b73a123cc
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@ -38,6 +38,7 @@ use timeline::TimeFns;
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#[derive(PartialEq, Clone, Copy)]
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enum Isa {
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Host,
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RiscV,
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CortexA9,
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}
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@ -184,11 +185,13 @@ impl Nac3 {
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#[new]
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fn new(isa: &str, py: Python) -> PyResult<Self> {
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let isa = match isa {
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"host" => Isa::Host,
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"riscv" => Isa::RiscV,
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"cortexa9" => Isa::CortexA9,
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_ => return Err(exceptions::PyValueError::new_err("invalid ISA")),
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};
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let time_fns: &(dyn TimeFns + Sync) = match isa {
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Isa::Host => &timeline::EXTERN_TIME_FNS,
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Isa::RiscV => &timeline::NOW_PINNING_TIME_FNS,
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Isa::CortexA9 => &timeline::EXTERN_TIME_FNS,
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};
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@ -410,10 +413,11 @@ impl Nac3 {
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passes.run_on(module);
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let (triple, features) = match isa {
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Isa::RiscV => (TargetTriple::create("riscv32-unknown-linux"), "+a,+m"),
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Isa::Host => (TargetMachine::get_default_triple(), TargetMachine::get_host_cpu_features().to_string()),
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Isa::RiscV => (TargetTriple::create("riscv32-unknown-linux"), "+a,+m".to_string()),
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Isa::CortexA9 => (
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TargetTriple::create("armv7-unknown-linux-gnueabihf"),
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"+dsp,+fp16,+neon,+vfp3",
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"+dsp,+fp16,+neon,+vfp3".to_string(),
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),
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};
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let target =
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@ -422,7 +426,7 @@ impl Nac3 {
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.create_target_machine(
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&triple,
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"",
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features,
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&features,
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OptimizationLevel::Default,
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RelocMode::PIC,
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CodeModel::Default,
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