linuswck
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linuswck commented on pull request M-Labs/artiq-zynq#268 2023-10-10 10:11:24 +08:00
Shuttler: Add Support on Kasli-Soc Platform

As kasli-soc has 4 drtio channels, drtio_destination needs to be manually specified to 5.

I think this could be automated?

Yes that should be automated. That should be a new PR…

linuswck created pull request M-Labs/artiq-zynq#268 2023-10-09 17:44:16 +08:00
Shuttler: Add Support on Kasli-Soc Platform
linuswck pushed to shuttler_kasli_soc_port at linuswck/artiq-zynq 2023-10-09 17:41:08 +08:00
a7cc4aa280 Firmware: Add drtio_eem.rs support
08469e46fe kasli_soc: Add support for shuttler on gateware
d4e8dd1554 zynq_clocking: add enable_sys5x option, IDELAYCTRL
Compare 3 commits »
linuswck pushed to shuttler_kasli_soc_port at linuswck/artiq-zynq 2023-10-09 16:57:34 +08:00
ce909a9e0c Firmware: Add drtio_eem.rs support
linuswck deleted branch efc_kasli_soc_port from linuswck/artiq-zynq 2023-10-09 16:40:37 +08:00
linuswck created branch shuttler_kasli_soc_port in linuswck/artiq-zynq 2023-10-09 16:39:14 +08:00
linuswck pushed to shuttler_kasli_soc_port at linuswck/artiq-zynq 2023-10-09 16:39:14 +08:00
linuswck pushed to efc_kasli_soc_port at linuswck/artiq-zynq 2023-10-09 16:37:28 +08:00
10320cdb9e Firmware: Add drtio_eem.rs support
bdeb40f999 enable_sys5x when efc is persent
ebe96e684a zynq_clocking: add enable_sys5x option, IDELAYCTRL
8eb359ee42 cargo fmt
7263862fd8 satellite: support optional args
Compare 22 commits »
linuswck created branch efc_kasli_soc_port in linuswck/artiq-zynq 2023-09-25 12:17:23 +08:00
linuswck pushed to efc_kasli_soc_port at linuswck/artiq-zynq 2023-09-25 12:17:23 +08:00
e451598a06 satman: fix dma reporting wrong destination
f4ceca464f drtio: change async messages to sync
f3dcd53086 firmware: fix zc706 compilation warnings
b3856e879b refactor `write_rustc_cfg_file()`
1ccae0d442 consolidate all `write..file()` into `config.py`
Compare 10 commits »
linuswck deleted branch efc_kasli_soc_port from M-Labs/artiq-zynq 2023-09-25 12:09:38 +08:00
linuswck pushed to efc_kasli_soc_port at M-Labs/artiq-zynq 2023-09-25 12:07:43 +08:00
linuswck created branch efc_kasli_soc_port in M-Labs/artiq-zynq 2023-09-25 12:07:42 +08:00
linuswck created pull request M-Labs/artiq-zynq#247 2023-08-28 13:04:43 +08:00
gt_drio: remame drtio_transceiver to gt_drtio
linuswck pushed to rename_drtio_transceiver_to_gt_drtio at linuswck/artiq-zynq 2023-08-28 12:59:15 +08:00
6057e4b27d gt_drio: remame drtio_transceiver to gt_drtio
linuswck created branch rename_drtio_transceiver_to_gt_drtio in linuswck/artiq-zynq 2023-08-28 12:55:14 +08:00
linuswck pushed to rename_drtio_transceiver_to_gt_drtio at linuswck/artiq-zynq 2023-08-28 12:55:14 +08:00
linuswck created repository linuswck/artiq-zynq 2023-08-28 12:48:10 +08:00
linuswck commented on issue M-Labs/artiq-zynq#246 2023-08-14 11:24:30 +08:00
satellite: SYS CLK did not switch

I'm pretty sure there is, it's just not obvious. Did you check the unisim model code?

I cannot find any info useful in the [Xilinx unisim library](https://github.com/Xilinx/XilinxUnisimLibrary…

linuswck commented on issue M-Labs/artiq-zynq#246 2023-08-11 15:35:37 +08:00
satellite: SYS CLK did not switch

Surely, there must be some information about it somewhere?

The max PLL Lock time is 1ms and this info locates inside the AC/DC Switching Characteristics [datasheet](https://docs.xilinx…