forked from M-Labs/thermostat
update to newer stm32-eth
This commit is contained in:
parent
1711feae84
commit
a3df2bc685
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@ -2,9 +2,9 @@
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# It is not intended for manual editing.
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# It is not intended for manual editing.
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dependencies = [
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dependencies = [
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"as-slice",
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"as-slice",
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@ -22,9 +22,9 @@ dependencies = [
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[[package]]
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[[package]]
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name = "bare-metal"
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name = "bare-metal"
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@ -37,9 +37,15 @@ dependencies = [
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[[package]]
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[[package]]
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[[package]]
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[[package]]
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[[package]]
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name = "bitflags"
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name = "bitflags"
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@ -70,20 +76,21 @@ checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
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[[package]]
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name = "cortex-m"
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"aligned",
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"bare-metal",
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"bitfield",
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"volatile-register",
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"volatile-register",
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]
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]
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[[package]]
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[[package]]
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name = "cortex-m-log"
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name = "cortex-m-log"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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"cortex-m",
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"cortex-m",
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"cortex-m-semihosting",
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"cortex-m-semihosting",
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@ -122,11 +129,11 @@ dependencies = [
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[[package]]
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[[package]]
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name = "embedded-hal"
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name = "embedded-hal"
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version = "0.2.4"
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"nb",
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"nb 0.1.3",
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@ -162,18 +169,18 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
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[[package]]
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"cfg-if",
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"cfg-if",
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name = "memchr"
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@ -183,15 +190,24 @@ checksum = "3728d817d99e5ac407411fa471ff9800a778d88a24685968b36824eaf4bee400"
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"nb 1.0.0",
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"memchr",
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"version_check",
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name = "num-traits"
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"autocfg",
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name = "proc-macro2"
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dependencies = [
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"unicode-xid",
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]
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name = "quote"
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name = "quote"
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version = "1.0.7"
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"proc-macro2",
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name = "stable_deref_trait"
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name = "stable_deref_trait"
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[[package]]
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name = "stm32-eth"
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name = "stm32-eth"
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version = "0.1.2"
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version = "0.2.0"
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source = "git+https://github.com/stm32-rs/stm32-eth.git#2c5dce379b85a31fb0b9c58a028b6454be1727aa"
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dependencies = [
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dependencies = [
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"aligned",
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"aligned",
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"log",
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"cortex-m",
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"smoltcp",
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"stm32f4xx-hal",
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name = "stm32f4"
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name = "stm32f4"
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version = "0.10.0"
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version = "0.11.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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dependencies = [
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name = "stm32f4xx-hal"
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name = "stm32f4xx-hal"
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version = "0.7.0"
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version = "0.8.3"
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source = "git+https://github.com/thalesfragoso/stm32f4xx-hal?branch=pwm-impl#cfd073e094daa9be9dd2b0a1f859a4e1c6be2b77"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b3a2f044469d1e3aff2cd02bee8b2724f3d5d91f3175e5d1ec99770320d16192"
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dependencies = [
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"bare-metal",
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"bare-metal",
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"cast",
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"cast",
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"cortex-m",
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"cortex-m",
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"cortex-m-rt",
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"cortex-m-rt",
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"embedded-hal",
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"embedded-hal",
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"nb",
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"nb 0.1.3",
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"rand_core",
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"rand_core",
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"stm32f4",
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name = "syn"
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version = "1.0.39"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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dependencies = [
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"proc-macro2",
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"quote",
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name = "typenum"
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version = "1.12.0"
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[[package]]
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name = "vcell"
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@ -387,9 +403,9 @@ checksum = "876e32dcadfe563a4289e994f7cb391197f362b6315dc45e8ba4aa6f564a4b3c"
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name = "version_check"
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name = "version_check"
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name = "void"
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name = "void"
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cortex-m = "0.6"
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cortex-m = "0.6"
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-log = { version = "0.6", features = ["log-integration"] }
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cortex-m-log = { version = "0.6", features = ["log-integration"] }
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stm32f4xx-hal = { version = "0.7", features = ["rt", "stm32f427"] }
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stm32f4xx-hal = { version = "0.8", features = ["rt", "stm32f427"] }
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stm32-eth = { version = "0.1.2", features = ["smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
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stm32-eth = { version = "0.2", features = ["stm32f427", "smoltcp-phy"], git = "https://github.com/stm32-rs/stm32-eth.git" }
|
||||||
smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
|
smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
|
||||||
hash2hwaddr = { version = "0.0", optional = true }
|
hash2hwaddr = { version = "0.0", optional = true }
|
||||||
bit_field = "0.10"
|
bit_field = "0.10"
|
||||||
|
@ -30,9 +30,6 @@ byteorder = { version = "1", default-features = false }
|
||||||
nom = { version = "5", default-features = false }
|
nom = { version = "5", default-features = false }
|
||||||
num-traits = { version = "0.2", default-features = false, features = ["libm"] }
|
num-traits = { version = "0.2", default-features = false, features = ["libm"] }
|
||||||
|
|
||||||
[patch.crates-io]
|
|
||||||
# TODO: pending https://github.com/stm32-rs/stm32f4xx-hal/pull/125
|
|
||||||
stm32f4xx-hal = { git = "https://github.com/thalesfragoso/stm32f4xx-hal", branch = "pwm-impl" }
|
|
||||||
|
|
||||||
[features]
|
[features]
|
||||||
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
|
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
|
||||||
|
|
|
@ -74,8 +74,6 @@ fn main() -> ! {
|
||||||
cp.SCB.enable_dcache(&mut cp.CPUID);
|
cp.SCB.enable_dcache(&mut cp.CPUID);
|
||||||
|
|
||||||
let dp = Peripherals::take().unwrap();
|
let dp = Peripherals::take().unwrap();
|
||||||
stm32_eth::setup(&dp.RCC, &dp.SYSCFG);
|
|
||||||
|
|
||||||
let clocks = dp.RCC.constrain()
|
let clocks = dp.RCC.constrain()
|
||||||
.cfgr
|
.cfgr
|
||||||
.use_hse(HSE)
|
.use_hse(HSE)
|
||||||
|
@ -91,7 +89,7 @@ fn main() -> ! {
|
||||||
|
|
||||||
timer::setup(cp.SYST, clocks);
|
timer::setup(cp.SYST, clocks);
|
||||||
|
|
||||||
let pins = Pins::setup(
|
let (pins, eth_pins) = Pins::setup(
|
||||||
clocks, dp.TIM1, dp.TIM3,
|
clocks, dp.TIM1, dp.TIM3,
|
||||||
dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG,
|
dp.GPIOA, dp.GPIOB, dp.GPIOC, dp.GPIOE, dp.GPIOF, dp.GPIOG,
|
||||||
dp.SPI2, dp.SPI4, dp.SPI5,
|
dp.SPI2, dp.SPI4, dp.SPI5,
|
||||||
|
@ -110,7 +108,7 @@ fn main() -> ! {
|
||||||
};
|
};
|
||||||
info!("Net hwaddr: {}", hwaddr);
|
info!("Net hwaddr: {}", hwaddr);
|
||||||
|
|
||||||
net::run(dp.ETHERNET_MAC, dp.ETHERNET_DMA, hwaddr, |iface| {
|
net::run(clocks, dp.ETHERNET_MAC, dp.ETHERNET_DMA, eth_pins, hwaddr, |iface| {
|
||||||
Server::<Session>::run(iface, |server| {
|
Server::<Session>::run(iface, |server| {
|
||||||
loop {
|
loop {
|
||||||
let instant = Instant::from_millis(i64::from(timer::now()));
|
let instant = Instant::from_millis(i64::from(timer::now()));
|
||||||
|
|
13
src/net.rs
13
src/net.rs
|
@ -5,11 +5,13 @@ use core::cell::RefCell;
|
||||||
use cortex_m::interrupt::Mutex;
|
use cortex_m::interrupt::Mutex;
|
||||||
use bare_metal::CriticalSection;
|
use bare_metal::CriticalSection;
|
||||||
use stm32f4xx_hal::{
|
use stm32f4xx_hal::{
|
||||||
|
rcc::Clocks,
|
||||||
stm32::{interrupt, Peripherals, ETHERNET_MAC, ETHERNET_DMA},
|
stm32::{interrupt, Peripherals, ETHERNET_MAC, ETHERNET_DMA},
|
||||||
};
|
};
|
||||||
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
|
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
|
||||||
use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
|
use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
|
||||||
use stm32_eth::{Eth, RingEntry, RxDescriptor, TxDescriptor};
|
use stm32_eth::{Eth, RingEntry, PhyAddress, RxDescriptor, TxDescriptor};
|
||||||
|
use crate::pins::EthernetPins;
|
||||||
|
|
||||||
/// Not on the stack so that stack can be placed in CCMRAM (which the
|
/// Not on the stack so that stack can be placed in CCMRAM (which the
|
||||||
/// ethernet peripheral cannot access)
|
/// ethernet peripheral cannot access)
|
||||||
|
@ -24,7 +26,9 @@ static NET_PENDING: Mutex<RefCell<bool>> = Mutex::new(RefCell::new(false));
|
||||||
|
|
||||||
/// Run callback `f` with ethernet driver and TCP/IP stack
|
/// Run callback `f` with ethernet driver and TCP/IP stack
|
||||||
pub fn run<F>(
|
pub fn run<F>(
|
||||||
|
clocks: Clocks,
|
||||||
ethernet_mac: ETHERNET_MAC, ethernet_dma: ETHERNET_DMA,
|
ethernet_mac: ETHERNET_MAC, ethernet_dma: ETHERNET_DMA,
|
||||||
|
eth_pins: EthernetPins,
|
||||||
ethernet_addr: EthernetAddress, f: F
|
ethernet_addr: EthernetAddress, f: F
|
||||||
) where
|
) where
|
||||||
F: FnOnce(EthernetInterface<&mut stm32_eth::Eth<'static, 'static>>),
|
F: FnOnce(EthernetInterface<&mut stm32_eth::Eth<'static, 'static>>),
|
||||||
|
@ -38,8 +42,11 @@ pub fn run<F>(
|
||||||
// Ethernet driver
|
// Ethernet driver
|
||||||
let mut eth_dev = Eth::new(
|
let mut eth_dev = Eth::new(
|
||||||
ethernet_mac, ethernet_dma,
|
ethernet_mac, ethernet_dma,
|
||||||
&mut rx_ring[..], &mut tx_ring[..]
|
&mut rx_ring[..], &mut tx_ring[..],
|
||||||
);
|
PhyAddress::_0,
|
||||||
|
clocks,
|
||||||
|
eth_pins,
|
||||||
|
).unwrap();
|
||||||
eth_dev.enable_interrupt();
|
eth_dev.enable_interrupt();
|
||||||
|
|
||||||
// IP stack
|
// IP stack
|
||||||
|
|
66
src/pins.rs
66
src/pins.rs
|
@ -2,7 +2,7 @@ use stm32f4xx_hal::{
|
||||||
adc::Adc,
|
adc::Adc,
|
||||||
hal::{blocking::spi::Transfer, digital::v2::OutputPin},
|
hal::{blocking::spi::Transfer, digital::v2::OutputPin},
|
||||||
gpio::{
|
gpio::{
|
||||||
AF5, Alternate, Analog,
|
AF5, Alternate, Analog, Floating, Input,
|
||||||
gpioa::*,
|
gpioa::*,
|
||||||
gpiob::*,
|
gpiob::*,
|
||||||
gpioc::*,
|
gpioc::*,
|
||||||
|
@ -19,9 +19,22 @@ use stm32f4xx_hal::{
|
||||||
stm32::{ADC1, GPIOA, GPIOB, GPIOC, GPIOE, GPIOF, GPIOG, SPI2, SPI4, SPI5, TIM1, TIM3},
|
stm32::{ADC1, GPIOA, GPIOB, GPIOC, GPIOE, GPIOF, GPIOG, SPI2, SPI4, SPI5, TIM1, TIM3},
|
||||||
time::U32Ext,
|
time::U32Ext,
|
||||||
};
|
};
|
||||||
|
use stm32_eth::EthPins;
|
||||||
use crate::channel::{Channel0, Channel1};
|
use crate::channel::{Channel0, Channel1};
|
||||||
|
|
||||||
|
|
||||||
|
pub type EthernetPins = EthPins<
|
||||||
|
PA1<Input<Floating>>,
|
||||||
|
PA2<Input<Floating>>,
|
||||||
|
PC1<Input<Floating>>,
|
||||||
|
PA7<Input<Floating>>,
|
||||||
|
PB11<Input<Floating>>,
|
||||||
|
PG13<Input<Floating>>,
|
||||||
|
PB13<Input<Floating>>,
|
||||||
|
PC4<Input<Floating>>,
|
||||||
|
PC5<Input<Floating>>,
|
||||||
|
>;
|
||||||
|
|
||||||
pub trait ChannelPins {
|
pub trait ChannelPins {
|
||||||
type DacSpi: Transfer<u8>;
|
type DacSpi: Transfer<u8>;
|
||||||
type DacSync: OutputPin;
|
type DacSync: OutputPin;
|
||||||
|
@ -86,7 +99,7 @@ impl Pins {
|
||||||
gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiof: GPIOF, gpiog: GPIOG,
|
gpioa: GPIOA, gpiob: GPIOB, gpioc: GPIOC, gpioe: GPIOE, gpiof: GPIOF, gpiog: GPIOG,
|
||||||
spi2: SPI2, spi4: SPI4, spi5: SPI5,
|
spi2: SPI2, spi4: SPI4, spi5: SPI5,
|
||||||
adc1: ADC1,
|
adc1: ADC1,
|
||||||
) -> Self {
|
) -> (Self, EthernetPins) {
|
||||||
let gpioa = gpioa.split();
|
let gpioa = gpioa.split();
|
||||||
let gpiob = gpiob.split();
|
let gpiob = gpiob.split();
|
||||||
let gpioc = gpioc.split();
|
let gpioc = gpioc.split();
|
||||||
|
@ -94,11 +107,6 @@ impl Pins {
|
||||||
let gpiof = gpiof.split();
|
let gpiof = gpiof.split();
|
||||||
let gpiog = gpiog.split();
|
let gpiog = gpiog.split();
|
||||||
|
|
||||||
Self::setup_ethernet(
|
|
||||||
gpioa.pa1, gpioa.pa2, gpioc.pc1, gpioa.pa7,
|
|
||||||
gpioc.pc4, gpioc.pc5, gpiob.pb11, gpiog.pg13,
|
|
||||||
gpiob.pb13
|
|
||||||
);
|
|
||||||
let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
|
let adc_spi = Self::setup_spi_adc(clocks, spi2, gpiob.pb10, gpiob.pb14, gpiob.pb15);
|
||||||
let adc_nss = gpiob.pb12.into_push_pull_output();
|
let adc_nss = gpiob.pb12.into_push_pull_output();
|
||||||
|
|
||||||
|
@ -151,13 +159,27 @@ impl Pins {
|
||||||
tec_u_meas_pin: tec_u_meas1_pin,
|
tec_u_meas_pin: tec_u_meas1_pin,
|
||||||
};
|
};
|
||||||
|
|
||||||
Pins {
|
let pins = Pins {
|
||||||
adc_spi, adc_nss,
|
adc_spi, adc_nss,
|
||||||
pins_adc,
|
pins_adc,
|
||||||
pwm,
|
pwm,
|
||||||
channel0,
|
channel0,
|
||||||
channel1,
|
channel1,
|
||||||
}
|
};
|
||||||
|
|
||||||
|
let eth_pins = EthPins {
|
||||||
|
ref_clk: gpioa.pa1,
|
||||||
|
md_io: gpioa.pa2,
|
||||||
|
md_clk: gpioc.pc1,
|
||||||
|
crs: gpioa.pa7,
|
||||||
|
tx_en: gpiob.pb11,
|
||||||
|
tx_d0: gpiog.pg13,
|
||||||
|
tx_d1: gpiob.pb13,
|
||||||
|
rx_d0: gpioc.pc4,
|
||||||
|
rx_d1: gpioc.pc5,
|
||||||
|
};
|
||||||
|
|
||||||
|
(pins, eth_pins)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Configure the GPIO pins for SPI operation, and initialize SPI
|
/// Configure the GPIO pins for SPI operation, and initialize SPI
|
||||||
|
@ -216,32 +238,6 @@ impl Pins {
|
||||||
|
|
||||||
(spi, sync)
|
(spi, sync)
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Configure the GPIO pins for Ethernet operation
|
|
||||||
fn setup_ethernet<M1, M2, M3, M4, M5, M6, M7, M8, M9>(
|
|
||||||
pa1: PA1<M1>, pa2: PA2<M2>, pc1: PC1<M3>, pa7: PA7<M4>,
|
|
||||||
pc4: PC4<M5>, pc5: PC5<M6>, pb11: PB11<M7>, pg13: PG13<M8>,
|
|
||||||
pb13: PB13<M9>
|
|
||||||
) {
|
|
||||||
// PA1 RMII Reference Clock - SB13 ON
|
|
||||||
pa1.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PA2 RMII MDIO - SB160 ON
|
|
||||||
pa2.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PC1 RMII MDC - SB164 ON
|
|
||||||
pc1.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PA7 RMII RX Data Valid D11 JP6 ON
|
|
||||||
pa7.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PC4 RMII RXD0 - SB178 ON
|
|
||||||
pc4.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PC5 RMII RXD1 - SB181 ON
|
|
||||||
pc5.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PB11 RMII TX Enable - SB183 ON
|
|
||||||
pb11.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PG13 RXII TXD0 - SB182 ON
|
|
||||||
pg13.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
// PB13 RMII TXD1 I2S_A_CK JP7 ON
|
|
||||||
pb13.into_alternate_af11().set_speed(VeryHigh);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
pub struct PwmPins {
|
pub struct PwmPins {
|
||||||
|
|
Loading…
Reference in New Issue